NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 307
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 307 of 890
- Download datasheet (7Mb)
Chipset Configuration Registers
7.1.73
Intel
®
ICH8 Family Datasheet
FDSW—Function Disable SUS Well
Offset Address: 3420h
Default Value:
14:5
6:1
Bit
Bit
15
4
3
2
1
0
7
0
IDE C3 HV IO Biasing Disable (IC3HVBD) — R/W.
0 = IDE HV IO Biasing is always on
1 = IDE HV IO Biasing is disabled on selected pins when in C3.
Reserved
PCI Express* RX Clock Gating Enable (PRXCGEN) — R/W.
0 = AFE Rx clock gating is disabled
1 = AFE Rx clock gating is enabled whenever all PCIe ports Rx are in squelch
DMI and PCI Express* RX Dynamic Clock Gate Enable — R/W.
0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled
1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled
PCI Express TX Dynamic Clock Gate Enable — R/W.
0 = PCI Express root port TX Dynamic Clock Gating is Disabled
1 = PCI Express root port TX Dynamic Clock Gating is Enabled
DMI TX Dynamic Clock Gate Enable — R/W.
0 = DMI TX Dynamic Clock Gating is Disabled
1 = DMI TX Dynamic Clock Gating is Enabled
PCI Express Root Port Static Clock Gate Enable — R/W.
0 = PCI Express root port Static Clock Gating is Disabled
1 = PCI Express root port Static Clock Gating is Enabled
Function Disable SUS Well Lockdown (FDSWL)— R/WL
0 = FDSW registers are not locked down
1 = FDSW registers are locked down
NOTE: This bit must be set when Intel
Reserved
LAN Disable — R/WL
0 = LAN is enabled
1 = LAN is Disabled.
If the Function Disable SUS Well Lockdown bit is set, this register is locked.
(ICH8DO and ICH8M-E Only).
0000h
Description
Description
®
Attribute:
Size:
Active Management Technology is enabled
R/W, RO
8-bit
307
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