NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 390

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

9.8.2
Table 114.
9.8.2.1
9.8.2.2
390
APM I/O Decode
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
APM Register Map
APM_CNT—Advanced Power Management Control Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
APM_STS—Advanced Power Management Status Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
Table 114
Address
7:0
7:0
Bit
Bit
B2h
B3h
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
register and is not affected by any other register or function (other than a PCI reset).
Used to pass an APM command between the OS and the SMI handler. Writes to this
port not only store data in the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
shows the I/O registers associated with APM support. This register space is
Mnemonic
APM_CNT
APM_STS
B2h
00h
No
Core
00h
No
Core
B3h
Advanced Power Management Control Port
Advanced Power Management Status Port
Register Name
Description
Description
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
R/W
8-bit
Legacy Only
R/W
8-bit
Legacy Only
Intel
®
Default
ICH8 Family Datasheet
00h
00h
Type
R/W
R/W