NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 313
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Gigabit LAN Configuration Registers
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
Intel
®
ICH8 Family Datasheet
RID—Revision Identification Register
(Gigabit LAN—D25:F0)
Offset Address: 08h
Default Value:
CC—Class Code Register
(Gigabit LAN—D25:F0)
Address Offset: 09h
Default Value:
CLS—Cache Line Size Register
(Gigabit LAN—D25:F0)
Address Offset: 0Ch
Default Value:
PLT—Primary Latency Timer Register
(Gigabit LAN—D25:F0)
Address Offset: 0Dh
Default Value:
HT—Header Type Register
(Gigabit LAN—D25:F0)
Address Offset: 0Eh
Default Value:
23:0
7:0
Bit
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Revision ID — RO. Refer to the Intel
Update for the value of the Revision ID Register.
Class Code— RO. This field indicates the device as an Ethernet Adapter.
020000h = Ethernet Adapter.
Cache Line Size — R/W. This field is implemented by PCI devices as a readwrite field for
legacy compatibility purposes but has no impact on any device functionality.
Latency Timer (LT) — RO. Hardwired to 0.
Header Type (HT) — RO.
00h = Indicates this is a single function device.
See bit description
020000h
00h
00h
00h
–
0Bh
®
Description
Description
Description
Description
Description
I/O Controller Hub 8 (ICH8) Family Specification
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
24 bits
R/W
8 bits
RO
8 bits
RO
8 bits
313
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