NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 475
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 475 of 890
- Download datasheet (7Mb)
SATA Controller Registers (D31:F2)
12.1.19
12.1.20
12.1.21
Note:
Intel
®
ICH8 Family Datasheet
INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch
Default Value:
INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh
Default Value:
IDE_TIM — IDE Timing Register (SATA–D31:F2)
Address Offset: Primary: 40h
Default Value:
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.
13:12
7:0
Bit
7:0
Bit
Bit
15
14
Interrupt Line — R/W. This field is used to communicate to software the interrupt line
that the interrupt pin is connected to.
Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Configuration
Registers: Offset 3100h:bits 11:8).
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or
Secondary decode.
0 = Disable.
1 = Enables the Intel
This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
NOTE: This bit affects SATA operation in both combined and non-combined ATA modes.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP) — R/W. The setting of these bits determines the number
of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h
for secondary).
See
00h
See Register Description
Secondary: 42h
0000h
Section 5.16
®
ICH8 to decode the associated Command Blocks (1F0–1F7h for
–
for more on ATA modes of operation.
41h
–
43h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
RO
8 bits
R/W
16 bits
475
Related parts for NH82801HEM S LB9B
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Intel
Datasheet:
Part Number:
Description:
Microprocessor: Intel Celeron M Processor 320 and Ultra Low Voltage Intel Celeron M Processor at 600MHz
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 82550 Fast Ethernet Multifunction PCI/CardBus Controller
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 64 Mbit. Access speed 150 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 100 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
DA28F640J5A-1505 Volt Intel StrataFlash Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 6300ESB I/O Controller Hub
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel 82801DB I/O Controller Hub (ICH4), Pb-Free SLI
Manufacturer:
Intel Corporation
Datasheet: