NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 695
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Intel
17.2.44
17.2.45
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
SDBDPL—Stream Descriptor Buffer Descriptor List Pointer
Lower Base Address Register
(Intel
Memory Address:Input Stream[0]: HDBAR + 98h Attribute:
Default Value:
SDBDPU—Stream Descriptor Buffer Descriptor List Pointer
Upper Base Address Register (Intel
Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 9Ch Attribute:
Default Value:
31:7
31:0
6:0
Bit
Bit
Buffer Descriptor List Pointer Lower Base Address — R/W. This field provides the
lower address of the Buffer Descriptor List. This value should only be modified when the
RUN bit is 0, or DMA transfer may be corrupted.
Hardwired to 0 forcing alignment on 128-B boundaries.
Buffer Descriptor List Pointer Upper Base Address — R/W. This field provides the
upper 32-bit address of the Buffer Descriptor List. This value should only be modified
when the RUN bit is 0, or DMA transfer may be corrupted.
®
High Definition Audio Controller—D27:F0)
Input Stream[1]: HDBAR + B8h
Input Stream[2]: HDBAR + D8h
Input Stream[3]: HDBAR + F8h
Output Stream[0]: HDBAR + 118h
Output Stream[1]: HDBAR + 138h
Output Stream[2]: HDBAR + 158h
Output Stream[3]: HDBAR + 178h
00000000h
Input Stream[1]: HDBAR + BCh
Input Stream[2]: HDBAR + DCh
Input Stream[3]: HDBAR + FCh
Output Stream[0]: HDBAR + 11Ch
Output Stream[1]: HDBAR + 13Ch
Output Stream[2]: HDBAR + 15Ch
Output Stream[3]: HDBAR + 17Ch
00000000h
Description
Description
§ §
Size:
Size:
®
High Definition Audio
R/W,RO
R/W
32 bits
32 bits
695
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