NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 362
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 362 of 890
- Download datasheet (7Mb)
9.4.10
362
ELCR1—Master Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)
Offset Address: 4D0h
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade
channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),
cannot be put into level mode.
2:0
Bit
7
6
5
4
3
IRQ7 ECL — R/W.
0 = Edge.
1 = Level.
IRQ6 ECL — R/W.
0 = Edge.
1 = Level.
IRQ5 ECL — R/W.
0 = Edge.
1 = Level.
IRQ4 ECL — R/W.
0 = Edge.
1 = Level.
IRQ3 ECL — R/W.
0 = Edge.
1 = Level.
Reserved. Must be 0.
00h
Description
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bits
Intel
®
ICH8 Family Datasheet
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