NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 331
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 331 of 890
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LPC Interface Bridge Registers (D31:F0)
9.1.17
Intel
®
ICH8 Family Datasheet
SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0)
Offset Address: 64h
Default Value:
Lockable:
5:2
1:0
Bit
7
6
Serial IRQ Enable (SIRQEN) — R/W.
0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
Serial IRQ Mode Select (SIRQMD) — R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for
Serial IRQ Frame Size (SIRQSZ) — RO. Fixed field that indicates the size of the
SERIRQ frame as 21 frames.
Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the
SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In
continuous mode, the ICH8 will drive the start frame for the number of clocks specified.
In quiet mode, the ICH8 will drive the start frame for the number of clocks specified
minus one, as the first clock was driven by the peripheral.
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
at least one frame after coming out of reset before switching back to Quiet
Mode. Failure to do so will result in the ICH8 not recognizing SERIRQ interrupts.
10h
No
Description
Attribute:
Size:
Power Well:
R/W, RO
8 bit
Core
331
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