NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 212
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 212 of 890
- Download datasheet (7Mb)
Table 85.
212
GateState1
GateState1
GateState1
GateState1
GateState2
GateState2
GateState2
GateState2
GateState2
Current
USB Legacy Keyboard State Transitions
State
64h / Write
64h / Write
64h / Write
60h / Write
60h / Read
64h / Read
64h / Read
60h / Read
64 / Write
Action
Not D1h
Not FFh
Value
Data
D1h
XXh
N/A
N/A
N/A
N/A
FFh
GateState1
GateState1
GateState2
State
Next
ILDE
IDLE
IDLE
IDLE
IDLE
IDLE
Cycle passed through to 8042, even if trap
enabled via Bit 3 in Config Register. No SMI#
generated. PSTATE remains 1. Stay in
GateState1 because this is part of the
double-trigger sequence.
Bit 3 in Config space determines if cycle
passed through to 8042 and if SMI#
generated. PSTATE goes to 0. If Bit 7 in
Config Register is set, then SMI# should be
generated.
This is an invalid sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Config Register. PSTATE
remains 1.
Standard end of sequence. Cycle passed
through to 8042. PSTATE goes to 0. Bit 7 in
Config Space determines if SMI# should be
generated.
Improper end of sequence. Bit 3 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
Just stay in same state. Generate an SMI# if
enabled in Bit 2 of Config Register. PSTATE
remains 1.
Improper end of sequence. Bit 1 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
Improper end of sequence. Bit 0 in Config
Register determines if cycle passed through
to 8042 and if SMI# generated. PSTATE goes
to 0. If Bit 7 in Config Register is set, then
SMI# should be generated.
Comment
Intel
®
Functional Description
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