NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 433
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
- Current page: 433 of 890
- Download datasheet (7Mb)
PCI-to-PCI Bridge Registers (D30:F0)
10.1.4
Note:
Intel
®
ICH8 Family Datasheet
PSTS—PCI Status Register (PCI-PCI—D30:F0)
Offset Address: 06h
Default Value:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Bit
15
4
3
2
1
0
Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI
Express* Base Specification, Revision 1.0a
Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification.
Bus Master Enable (BME) — R/W.
0 = Disable
1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.
Memory Space Enable (MSE) — R/W. Controls the response as a target for memory
cycles targeting PCI.
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles
targeting PCI.
0 = Disable
1 = Enable
Detected Parity Error (DPE) — R/WC.
0 = Parity error Not detected.
1 = Indicates that the ICH8 detected a parity error on the internal backbone. This bit
gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set.
0010h
–
07h
Description
Description
Attribute:
Size:
R/WC, RO
16 bits
433
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