NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 363
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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LPC Interface Bridge Registers (D31:F0)
9.4.11
Intel
®
ICH8 Family Datasheet
ELCR2—Slave Controller Edge/Level Triggered Register
(LPC I/F—D31:F0)
Offset Address: 4D1h
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Bit
7
6
5
4
3
2
1
0
IRQ15 ECL — R/W.
0 = Edge
1 = Level
IRQ14 ECL — R/W.
0 = Edge
1 = Level
Reserved. Must be 0.
IRQ12 ECL — R/W.
0 = Edge
1 = Level
IRQ11 ECL — R/W.
0 = Edge
1 = Level
IRQ10 ECL — R/W.
0 = Edge
1 = Level
IRQ9 ECL — R/W.
0 = Edge
1 = Level
Reserved. Must be 0.
00h
Description
Attribute:
Size:
R/W
8 bits
363
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