NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 431

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

PCI-to-PCI Bridge Registers (D30:F0)
10
10.1
Note:
.
Table 118.
Intel
®
ICH8 Family Datasheet
PCI-to-PCI Bridge Registers
(D30:F0)
The ICH8 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements
the buffering and control logic between PCI and the backbone. The arbitration for the
PCI bus is handled by this PCI device.
PCI Configuration Registers (D30:F0)
Address locations that are not shown should be treated as Reserved (see
for details).
PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 1 of 2)
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h–0Bh
0Dh
0Eh
18h–1Ah
1Bh
1Ch–1Dh
1Eh–1Fh
20h–23h
24h–27h
28h–2Bh
2Ch–2Fh
34h
3Ch-3Dh
3Eh–3Fh
40h–41h
44h–47h
48h–4Bh
Offset
VID
DID
PCICMD
PSTS
RID
CC
PMLT
HEADTYP
BNUM
SMLT
IOBASE_LIMIT
SECSTS
MEMBASE_LIMIT
PREF_MEM_BASE
_LIMIT
PMBU32
PMLU32
CAPP
INTR
BCTRL
SPDH
DTC
BPS
Mnemonic
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Primary Master Latency Timer
Header Type
Bus Number
Secondary Master Latency Timer
I/O Base and Limit
Secondary Status
Memory Base and Limit
Prefetchable Memory Base and
Limit
Prefetchable Memory Upper 32 Bits
Prefetchable Memory Limit Upper
32 Bits
Capability List Pointer
Interrupt Information
Bridge Control
Secondary PCI Device Hiding
Delayed Transaction Control
Bridge Proprietary Status
Register Name
See register
See register
00060401h
00000000h
00010001h
00000000h
00000000h
00000000h
00000000h
description
description
000000h
Default
8086h
0000h
0010h
0000h
0280h
0000h
0000h
00h
81h
00h
50h
00h
Section 6.2
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
Type
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
431