NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 430
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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9.10.13
430
GPIO_USE_SEL Override Register (HIGH)—GPIO Use
Select Override Register High
Offset Address: GPIOBASE +3Ch
Default Value:
Lockable:
31:0
Bit
GPIO_USE_SEL Override [63:32] — R/W. Each bit in this field corresponds to one
of the Host GPIO indexed signals. A 1b in this field forces the corresponding Host
Signal used as native function mode, regardless of the Host GPIO_USE_SEL register
bit. A 0b in this field leaves the determination of the pin usage to the GPIO_USE_SEL
register.
Once a bit is set to 1b, it can only be cleared a reset. Bits 31:24 and 15:8 are cleared
by RSMRST# and CF9h events. Bits 23:16 and 7:0 are cleared by PLTRST# events.
If the corresponding GPIO is not multiplexed with Native functionality or not
implemented at all, this bit has no effect.
This register corresponds to GPIO[55:48, 43:32]. Bit 0 corresponds to GPIO32.
00000000h
No
Attribute:
Size:
Power Well:
§ §
Description
LPC Interface Bridge Registers (D31:F0)
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Intel
®
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