NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 661

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

Intel
17.1.40
17.1.41
17.1.42
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
PVCSTS—Port VC Status Register
(Intel
Address Offset: 10Eh–10Fh
Default Value:
VC0CAP—VC0 Resource Capability Register
(Intel
Address Offset: 110h–113h
Default Value:
VC0CTL—VC0 Resource Control Register
(Intel
Address Offset: 114h–117h
Default Value:
31:24
22:16
30:27
26:24
23:20
19:17
15:1
13:8
15:8
7:0
7:0
Bit
Bit
Bit
23
15
14
31
16
0
Reserved.
VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not
present.
Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for
endpoint devices
Reserved.
Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint
devices
Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for
endpoint devices
Reserved.
Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for endpoint
devices
VC0 Enable — RO. Hardwired to 1 for VC0.
Reserved.
VC0 ID — RO. Hardwired to 0 since the first VC is always assigned as VC0.
Reserved.
Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
Reserved.
TC/VC0 Map — R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits
7:1 are implemented as R/W bits.
®
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
0000h
00000000h
800000FFh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
16 bits
RO
32 bits
R/W, RO
32 bits
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