NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 471

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
12.1.9
12.1.10
.
12.1.11
.
Intel
®
ICH8 Family Datasheet
PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)
Address Offset: 0Dh
Default Value:
PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2)
Address Offset: 10h
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2)
Address Offset: 14h
Default Value:
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
31:16
31:16
15:3
15:2
2:1
Bit
Bit
7:0
Bit
0
1
0
Reserved
Base Address — R/W. This field provides the base address of the I/O space
(8 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Reserved
Base Address — R/W. This field provides the base address of the I/O space
(4 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated
as a PCI device, so it does not need a Master Latency Timer.
00h
00000001h
00000001h
–
–
13h
17h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W, RO
32 bits
R/W, RO
32 bits
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