NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 592
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NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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15.1.16
15.1.17
592
PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F7, D26:F7)
Address Offset: 50h
Default Value:
NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F7, D26:F7)
Address Offset: 51h
Default Value:
7:0
Bit
7:0
Bit
Power Management Capability ID — RO. A value of 01h indicates that this is a PCI
Power Management capabilities field.
Next Item Pointer 1 Value — R/W (special). This register defaults to 58h, which
indicates that the next capability registers begin at configuration offset 58h. This
register is writable when the WRT_RDONLY bit (D29:F7, D26:F7:80h, bit 0) is set. This
allows BIOS to effectively hide the Debug Port capability registers, if necessary. This
register should only be written during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Only values of 58h (Debug Port
visible) and 00h (Debug Port invisible) are expected to be programmed in this register.
NOTE: Register not reset by D3-to-D0 warm reset.
01h
58h
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
RO
8 bits
R/W (special)
8 bits
Intel
®
ICH8 Family Datasheet
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