NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 689

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

Intel
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
Bit
1
0
Stream Run (RUN) — R/W.
0 = Disable. When cleared to 0, the DMA engine associated with this input stream will
1 = Enable. When set to 1, the DMA engine associated with this input stream will be
Stream Reset (SRST) — R/W.
0 = Writing a 0 causes the corresponding stream to exit reset. When the stream
1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor
be disabled. The hardware will report a 0 in this bit when the DMA engine is
actually stopped. Software must read a 0 from this bit before modifying related
control registers or restarting the DMA engine.
enabled to transfer data from the FIFO to the main memory. The SSYNC bit must
also be cleared in order for the DMA engine to run. For output streams, the
cadence generator is reset whenever the RUN bit is set.
hardware is ready to begin operation, it will report a 0 in this bit. Software must
read a 0 from this bit before accessing any of the stream registers.
registers (except the SRST bit itself) and FIFO’s for the corresponding stream are
reset. After the stream hardware has completed sequencing into the reset state, it
will report a 1 in this bit. Software must read a 1 from this bit to verify that the
stream is in reset. The RUN bit must be cleared before SRST is asserted.
Description
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