NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 388
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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9.8.1.10
388
QRT_CNT1 (PM—D31:F0): Quick Resume Technology Control 1
Register (Intel
Offset Address: B1h
Default Value:
Lockable:
Power Well:
15:10
5:4
3:2
Bit
9
8
7
6
1
0
Reserved
SMI_OPTION_CNT—R/W: When this bit is set to 1 the platform generates an SMI
when an QRT event occurs (rather than generating an SCI). The SMI handler can cause
the SCI by setting the SCI_NOW_CNT.
SCI_NOW_CNT—WO: When software writes a ‘1’ to this bit, it causes
QRT_SCI_NOW_STS (Offset B0:Bit 4) to assert (which can be enabled to cause an
SCI). This allows the SMI handler to cause the SCI.
PWRBTN_INT_EN—R/W: When this bit is set to 1, the QRT logic is enabled to
intercept the power button to cause the QRT SMI or SCI, and not immediately setting
the PWRBTN_STS bit. The QRT software will later set the PWRBTN_STS bit by setting
the PWRBTN_EVNT bit.
NOTE: This bit is effective only in S0.
PWRBTN_EVNT—WO: When this bit is set to 1 by software, the PWRBTN_STS bit is
set to 1. This allows software to communicate PWR_BTN event to OS.
NOTES:
1.
2.
QRT_STATE1_CNT[1:0]—R/W: These bits controls the QRT_STATE1 pin. The
QRT_STATE[1:0] pins can be used to control a multi color LED to indicate the platform
power states to user. If QRT_LED_OWN is 0 then these bits have no impact.
00 = Low
01 = High
10 = Blinking. Note that the blink rate is ~ 1 Hz
11 = Reserved. Software must not set this combination
QRT_STATE0_CNT[1:0]—R/W: These bits controls the QRT_STATE0 pin. The
QRT_STATE[1:0] pins can be used to control a multi-color LED to indicate the platform
power states to user. If QRT_LED_OWN is 0 then these bits have no impact.
00 = Low
01 = High
10 = Blinking. Note that the blink rate is ~ 1 Hz
11 = Reserved. Software must not set this combination
QRT_LED_OWN—R/W: Software sets this bit to 1 to configure the multiplexed pins to
be QRT_STATE[1:0] rather than GPIO[28:27].
Reserved
Power Button override still possible
Software does not need to clear this bit, as it is treated as an event
0000h
No
Resume
®
ICH8DH Only)
Attribute:
Size:
Usage:
Description
LPC Interface Bridge Registers (D31:F0)
R/W
16-bit
Quick Resume Technology
Intel
®
ICH8 Family Datasheet
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