TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet
TMP86xy48UG/FG
Specifications of TMP86xy48UG/FG
Related parts for TMP86xy48UG/FG
TMP86xy48UG/FG Summary of contents
Page 1
Bit Microcontroller TLCS-870/C Series TMP86FM48 ...
Page 2
... It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “ ...
Page 3
Date Revision 2007/8/24 1 2008/8/29 2 Revision History First Release Contents Revised ...
Page 4
Caution in Setting the UART Noise Rejection Time When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com- bination "O" is available but please do not select the combination "–". The ...
Page 5
... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C • ...
Page 6
Serial interface • UART/SIO: 1ch • SIO: 1ch • bus: 1ch 2 ♦ 10-bit successive approximation type AD converter • Analog input ♦ Four Key-on wake-up pins ♦ Dual clock operation • Single/dual-clock mode ♦ ...
Page 7
Pin Assignments (Top view) LQFP64-P-1010-0.50E QFP64-P-1414-0.80C P80 P81 P82 P83 P84 P85 P86 P87 P30 P31 P32 P33 P34 P35 P36 P37 86FM48-3 TMP86FM48 ...
Page 8
Block Diagram Power VDD supply VSS Reset input RESET System control circuit TEST pin TEST Standby control circuit (Key-on wake-up) Timing generator Resonator High XIN connecting frequency XOUT pins Low frequency Address/Data bus P2 P77 (AIN17) P22 to P20 P70 ...
Page 9
Pin Functions (1/2) Pin Name Input/Output P07 ( ) SCK1 I/O (I/O) P06 (TXD, SO1) I/O (Output) P05 (RXD, SI1) I/O (Input) P04 I/O P03 (TC2) I/O (Input) P02 (INT2) I/O (Input) P01 (INT1) I/O (Input) P00 ( ) INT0 ...
Page 10
Pin Functions (2/2) Pin Name Input/Output P77 (AIN17) I/O (Input) P76 (AIN16) I/O (Input) P75 (AIN15) I/O (Input) P74 (AIN14) I/O (Input) P73 (AIN13) I/O (Input) P72 (AIN12) I/O (Input) P71 (AIN11) I/O (Input) P70 (AIN10) I/O (Input) P87 to ...
Page 11
Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, ...
Page 12
Data Memory (RAM) The TMP86FM48 has 2048 bytes of internal RAM. The first 192 bytes (0040 the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents ...
Page 13
System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Clock generator XIN High-frequency clock oscillator XOUT XTIN Low-frequency clock oscillator XTOUT 1.4.1 Clock Generator The clock generator generates the ...
Page 14
Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. a. Generation of main system clock b. ...
Page 15
TBTCR (DVOEN) (DVOCK) (0036 ) H Selection of input to the 7th DV7CK stage of the divider Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” on DV7CK ...
Page 16
Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. There are two operating modes: single-clock and dual-clock. These modes are controlled ...
Page 17
Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and ...
Page 18
SLEEP2 mode The SLEEP2 mode is the IDLE mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-frequency clock. g. SLEEP0 ...
Page 19
SYSCR2<TGHALT> = “1” SYSCR2<IDLE> = “1” IDLE1 mode Interrupt (a) Single clock mode SYSCR2<XTEN> = “0” SYSCR2<IDLE> = “1” IDLE2 mode Interrupt SYSCR2<SYSCK> = “0” SYSCR2<IDLE> = “1” SLEEP2 mode Interrupt SYSCR2<XTEN> = “1” SYSCR2<IDLE> = “1” SLEEP1 mode Interrupt ...
Page 20
System Control Register 1 SYSCR1 (0038 ) STOP RELM RETM H STOP STOP mode start Release method for STOP pin RELM (P20) Operating mode after STOP RETM mode Port output during STOP OUTEN mode Warm-up time at ...
Page 21
Operating Mode Control (1) STOP mode STOP mode is controlled by the system control register 1, the key-on wake-up input (STOP0 to STOP3) which is controlled by the STOP mode release control register (STOPCR). The pin is also used ...
Page 22
Example 1: Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS SET Example 2: Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD SET SINT5: RETI pin STOP XOUT ...
Page 23
STOP pin XOUT pin NORMAL operation STOP mode started by the program. Note: When the STOP mode is started with the EEPCR<MNPWDW> = “1”, the CPU wait for stabilizing of the power supply of Flash control circuit is executed after ...
Page 24
Table 1.4.1 Warm-up Time Example ( 16.0 MHz 32.768 kHz) Warm-up Time [ms] (Note 2) WUT Return to NORMAL Mode 12.288 + (0.064) 00 4.096 + (0.064) 01 3.072 + (0.064) 10 1.024 + (0.064) 11 ...
Page 25
Figure 1.4.10 STOP Mode Start/Release (When EEPCR<MNPWDW> = “0”) 86FM48-21 TMP86FM48 2007-08-24 ...
Page 26
Figure 1.4.11 STOP Mode Start/Release (When EEPCR<MNPWDW> = “1”) 86FM48-22 TMP86FM48 2007-08-24 ...
Page 27
IDLE1/2 mode, SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. a. Operation of the CPU and watchdog timer (WDT) is halted. ...
Page 28
Start the IDLE1/2 and SLEEP1/2 modes When IDLE1/2 and SLEEP1/2 modes start, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode. These modes ...
Page 29
Figure 1.4.13 IDLE1/2, SLEEP1/2 Mode Start/Release 86FM48-25 TMP86FM48 2007-08-24 ...
Page 30
IDLE0, SLEEP0 mode (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. a. Timing generator ...
Page 31
Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. When IDLE0 and SLEEP0 modes start, set SYSCR2<TGHALT> to “1”. • Release the IDLE0 and SLEEP modes IDLE0 and SLEEP0 modes include a normal release ...
Page 32
Figure 1.4.15 IDLE0, SLEEP0 Mode Start/Release 86FM48-28 TMP86FM48 2007-08-24 ...
Page 33
SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter (TC2). a. Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2<SYSCK> to ...
Page 34
Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm-up) has been taken by the timer/counter 2 (TC2), clear SYSCR2<SYSCK> to switch the main system clock to the ...
Page 35
Figure 1.4.16 Switching between the NORMAL2 and SLOW Modes 86FM48-31 TMP86FM48 2007-08-24 ...
Page 36
Interrupt Control Circuit The TMP86FM48 has a total (Reset is excluded interrupt source: 5 externals and 15 internals the internal sources are non-maskable interrupts, and the rest of them are maskable interrupts. Interrupt sources are ...
Page 37
Figure 1.5.1 Interrupt Controller Block Diagram 86FM48-33 TMP86FM48 2007-08-24 ...
Page 38
Interrupt latches ( interrupt latch is provided for each interrupt source, except for a software interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to accept the ...
Page 39
Individual interrupt enable flags (EF Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit ...
Page 40
Interrupt Latches ILH, ILL (003C , 003D ) ILE (002E ) Interrupt Latches 23 2 Note 1: IL and IL are prohibited from clearing. ...
Page 41
Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles (4 µs at 8.0 MHz) after ...
Page 42
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address 03 FFF0 FFF1 maskable interrupt is not accepted until the IMF is set to ...
Page 43
Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example: Save/store register using data transfer instructions PINTxx: LD (interrupt processing) LD Main task Interrupt acceptance Interrupt return Saving/restoring general-purpose registers ...
Page 44
Example 1: Returning from address trap interrupt (INTATRAP) service program PINTxx: POP WA LD WA, Return Address PUSH WA (interrupt processing) RETN Example 2: Restarting without returning interrupt (In this case, PSW (includes IMF) before interrupt acceptance is discarded.) PINTxx ...
Page 45
Software Interrupt (INTSW) Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the [SWI] instruction only for detection of the address error or for debugging. (1) Address error detection ...
Page 46
Secondary Source Pin Function Pin INT 0 INT0 P00 INT1 INT1 P01 INT2 INT2 P02 INT3 INT3 P14/TC3 P20/ INT5 INT 5 STOP Note noiseless signal is input to the external interrupt pin in the NORMAL 1/2 ...
Page 47
Reset Circuit The TMP86FM48 has four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Table 1.6.1 shows on-chip hardware initialization by reset action. Since the ...
Page 48
Address-Trap-Reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”) or the SFR area, address-trap-reset and the ...
Page 49
On-Chip Peripherals Functions 2.1 Special Function Register (SFR) The TMP86FM48 adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000 to ...
Page 50
Address Read 1F80 SBISR (SBI status) DD UARTSR (UART status RDBUF (UART received data buffer EEPSR (FLASH status) E2 EEPEVA (FLASH write emulation time control ...
Page 51
I/O Ports The TMP86FM48 has 8 parallel input/output ports (54 pins) as follows. Primary Function Port P0 8-bit I/O port Port P1 8-bit I/O port Port P2 3-bit I/O port Port P3 8-bit I/O port Port P5 3-bit I/O ...
Page 52
Port P0 (P07 to P00) Port 8-bit input/output port which is also used as an external interrupt input, serial interface input/output, timer/counter input and UART input/output. It can be selected whether output circuit of P0 port ...
Page 53
Port P1 (P17 to P10) Port 8-bit input/output port which is also used as an external interrupt input, serial interface input/output and timer/counter input/output. It can be selected whether output circuit of P1 port is CMOS ...
Page 54
Port P2 (P22 to P20) Port 3-bit input/output port also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. It can be selected whether output circuit ...
Page 55
Data input (P20PRD) , input INT5 STOP STOP P2OUTCR P2OUTCR input Data input (P20) Data output (P20) Note: Port P20 is used as STOP becomes High-Z state P2DR (0002 ) H R/W P2OUTCR (1FE4 ) H Port ...
Page 56
Port P3 (P37 to P30) Port 8-bit input/output port. It can be selected whether output circuit of P3 port is CMOS output or a sink open drain individually, by setting P3OUTCR. (N-ch high current output) When ...
Page 57
Port P5 (P52 to P50) Port 3-bit input/output port which is also used as a timer/counter output, divider output and serial bus interface input/output. (N-ch high current output) It can be selected whether output circuit of ...
Page 58
Port P6 (P67 to P60) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also used as an analog input and key-on wake-up input. Input/output ...
Page 59
Analog input AINDS SAIN STOPkEN STOP OUTEN P6CR2j D P6CR2j input P6CR1j D P6CR1j input STOPk input Data input (P6DR) Data output (P6DR P6DR P67 P66 P65 AIN07 AIN06 AIN05 (0006 ) H STOP3 STOP2 STOP1 R/W ...
Page 60
Port P7 (P77 to P70) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P7 is also used as an analog input. Input/output mode is specified by ...
Page 61
Analog input AINDS SAIN STOP OUTEN P7CR2i D P7CR2i input P7CR1i D P7CR1i input Data input (P7DR) Data output (P7DR P7DR P77 P76 P75 AIN17 AIN16 AIN15 (0007 ) H R/W P7CR1 (1FE5 ) H Port P7 ...
Page 62
Port P8 (P87 to P80) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit. Input/output mode is specified by the P8 control register (P8CR). When used as an ...
Page 63
Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). An INTTBT is generated on the first falling edge of source clock (The ...
Page 64
TBTCR (0036 ) (DVOEN) (DVOCK) H Time base timer TBTEN enable/disable Time base timer interrupt TBTCK frequency select [Hz] Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care Figure 2.3.2 Time Base Timer Control ...
Page 65
Watchdog Timer (WDT) The watchdog timer is a fail-safe system to rapidly detect the CPU malfunctions such as endless looping caused by noise or the like, or deadlock and resume the CPU to the normal state. The watchdog timer ...
Page 66
Watchdog Timer Control Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows. 1. Setting the ...
Page 67
Watchdog Timer Register 1 WDTCR1 (0034 ) (ATAS) (ATOUT) WDTEN H Watchdog timer WDTEN enable/disable Watchdog timer WDTT detection time [s] Watchdog timer WDTOUT output select Note 1: WDTOUT cannot be set to “1” by program after ...
Page 68
Example: Disables watchdog timer Table 2.4.1 Watchdog Timer Detection Time (Example MHz 32.768 kHz) WDTT DV7CK = 524.288 m 10 131.072 m 11 2.4.3 Watchdog Timer Interrupt (INTWDT) This is a non-maskable ...
Page 69
Address Trap The watchdog timer control register 1, 2 shares its addresses with the control registers in case of address trap. These control registers for address trap are shown on Figure 2.5.1. Watchdog Timer Control Register 1 WDTCR1 7 ...
Page 70
Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from pin P51 ( should be set to “1”. Note: Selection of divider output ...
Page 71
Timer/Counter 1 2.7.1 Configuration Figure 2.7.1 Timer/Counter 1 (TC1) 86FM48-67 TMP86FM48 2007-08-24 ...
Page 72
Control The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB TC1DRA TC1DRAH (0021H) (0021,0020H) R/W TC1DRBH (0023H) TC1DRB (0023,0022H) R/W Note: TC1DRB should not ...
Page 73
Note 10: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB ...
Page 74
Command start Source clock Up counter TC1DRA ? n INTTC1 interrupt Source clock m − − counter m − 1 TC1DRB ? ACAP1 n − Match detect Counter ...
Page 75
External trigger timer mode In this mode, counting up is started by an external trigger. This trigger is the edge of the TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source clock is ...
Page 76
Count start TC1 pin input Trigger Internal clock Up counter 0 TC1DRA ? n INTTC1 interrupt Count start TC1 pin input Trigger Internal clock Up counter TC1DRA n INTTC1 interrupt Figure 2.7.4 External Trigger Timer Mode Timing ...
Page 77
Table 2.7.2 Timer/Counter 1 External Clock Source NORMAL1/2, IDLE1/2 Mode “H” width “L” width (4) Window mode In this mode, counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TC1 ...
Page 78
Pulse width measurement mode In this mode, counting is started by the external trigger (Set to external trigger start by TC1CR<TC1S>). The trigger can be selected either the rising or falling edge of the TC1 pin input. The source ...
Page 79
Count start TC1 pin Trigger input Internal clock Up counter TC1DRB INTTC1 interrupt Count start TC1 pin input Internal clock Up counter TC1DRB INTTC1 interrupt Figure 2.7.7 Pulse Measurement Mode Timing Chart n − ...
Page 80
Programmable pulse generate (PPG) output mode The PPG output mode is intended to output pulses having an arbitrary duty cycle selected using two timer registers. The timer starts at an edge (Rising or falling edge, that is, the same ...
Page 81
TFF1 TC1CR write strobe Internal reset Match with TC1DRB Match with TC1DRA INTTC1 interrupt MPPG1 Command start Internal clock Up counter TC1DRB n Match TC1DRA m pin output PPG INTTC1 interrupt Count start TC1 pin input Trigger ...
Page 82
Timer/Counter 2 2.8.1 Configuration (Note 2) MPX Port TC2 pin fc fc/2 or fs/2 B Timer/event 8 fc/2 C counter 3 fc ...
Page 83
Control The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). Reset does not affect TC2DR TC2DR TC2DRH (0025H) (0025, 0024H) R/W TC2CR ...
Page 84
Function The timer/counter 2 has three operating modes: timer, event counter and window modes. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up ...
Page 85
Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up counter match is found, an INTTC2 interrupt ...
Page 86
Window mode In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input (Window pulse) is “H” level. The contents of TC2DR are compared with the contents of up counter. If ...
Page 87
Timer/Counter 3 2.9.1 Configuration TC3 pin Port MPX (Note fc fc fc fc fc/2 ...
Page 88
Control The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB TC3DRA (0010H) R TC3DRB (0011H) Read only TC3CR 7 6 ...
Page 89
Function The timer/counter 3 has three operating modes: timer, event counter, and capture mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC3DRA are compared with the contents of up ...
Page 90
Event counter mode In this mode, events are counted on the edge of the TC3 pin input. The counter counts up on the rising edge of the TC3 pin input and when its value matches the TC3DRA set value, ...
Page 91
Capture mode In this mode, the pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals or distinguishing AC 50/60 Hz, etc. Once command ...
Page 92
Figure 2.9.3 Capture Mode Timing Chart 86FM48-88 TMP86FM48 2007-08-24 ...
Page 93
Timer/Counter 5 2.10.1 Configuration TC5S MPX fc fc/2 Source 3 D fc/2 clock 8-bit up counter fc Port S TC5 ...
Page 94
Control The timer/counter 5 is controlled by a timer/counter 5 control register (TC5CR) and an 8-bit timer register 5 (TC5DR). Reset does not affect TC5DR. TC5DR (0015H) R TC5CR TC5S (0014H) ...
Page 95
Function The timer/counter 5 has four operating modes: timer, event counter, programmable divider output, and PWM output mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC5DR is compared with ...
Page 96
Programmable divider output (PDO) mode The programmable divider output (PDO) mode is intended to output a pulse having a duty cycle of about 50%. The counter counts internal source clock. If the timer value matches TC5DR, ...
Page 97
Pulse width modulation (PWM) output mode The pulse width modulation (PWM) output mode is intended to output pulses at constant intervals with a resolution of 8 bits. The counter counts up on the internal source clock. If the timer ...
Page 98
UART (Asynchronous serial interface) The TMP86FM48 has 1 channel of UART (Asynchronous serial interface). The UART is connected to external devices via RXD and TXD. RXD is also used as P05; TXD, as P06. To use P05 or P06 ...
Page 99
Control UART is controlled by the UART control registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR). UART control register UARTCR1 (1FDD ) TXE RXE STBT H TXE Transfer operation ...
Page 100
UARTSR (1FDD ) PERR FERR OERR H PERR Parity error flag FERR Framing error flag OERR Overrun error flag RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty flag Note: When ...
Page 101
Transfer Data Format In UART, a one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the transfer data. ...
Page 102
Transfer Rate The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate shown as follows. BRG 16 MHz 000 76800 [baud] 001 38400 010 19200 011 9600 100 4800 101 2400 When TC5 is ...
Page 103
STOP Bit Length Select a transmit stop bit length ( bits) by UARTCR1<STBT>. 2.11.7 Parity Set parity/no parity by UARTCR1<PE>; set parity type (odd- or even-numbered) by UARTCR1<EVEN>. 2.11.8 Transmit/Receive (1) Data transmit Set UARTCR1<TXE> to “1”. ...
Page 104
Status Flag/Interrupt Signal (1) Parity error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is ...
Page 105
Overrun error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF are not ...
Page 106
Transmit data buffer empty When no data is in the transmit buffer TDBUF, UARTSR<TBEP> is set to “1”, that is, when data in TDBUF are transferred to the transmit shift register and data transmit starts, transmit data buffer empty ...
Page 107
Serial Bus Interface (SBI-ver. D) The TMP86FM48 has a 1-channel serial bus interface which employs an I system by Philips). The serial interface is connected to external devices through P51 (SDA) and P50 (SCL). The serial bus interface pins ...
Page 108
Software Reset A serial bus interface circuit has a software reset function, when a serial bus interface circuit is locked by an external noise, etc. To reset the serial bus interface circuit, write “01”, “10” into the SWRST (Bit1, ...
Page 109
I C Bus Control The following registers are used to control the serial bus interface (SBI) and monitor the operation status of the I Serial Bus Interface Control Register SBICRA (1FD9H Number ...
Page 110
Serial Bus Interface Control Register SBICRB (1FDCH) MST TRX BB Master/slave selection MST TRX Transmitter/receiver selection BB Start/stop generation PIN Cancel interrupt service request Serial bus interface operating SBIM mode selection SWRST1 SWRST0 Software reset start ...
Page 111
Acknowledgement mode specification Acknowledgment mode (ACK = “1” set the device as an acknowledgment mode, the ACK (Bit4 in SBICRA) should be set to “1”. When a serial bus interface circuit is a master mode, an additional ...
Page 112
Four or more machine cycles are required for both high and low levels of pulse width in the external clock which is input from SCL pin. Note: Since the I high-speed mode, do not set SCK as the frequency that ...
Page 113
SCL pin to the low level. The clock pulse on the bus is determined by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected ...
Page 114
Start/stop condition generation When the BB (Bit5 in SBISR) is “0”, a slave address and a direction bit which are set to the SBIDBR are output on a bus after generating a start condition by writing “1” to the ...
Page 115
Setting bus mode 2 The SBIM (Bit3 and 2 in SBICRB) is used to set I Set the SBIM to “10” in order to set I confirm serial bus interface pins in a high level, and ...
Page 116
SCL pin 1 2 Master A SDA pin D7A D6A D5A SCL pin 1 2 Master B SDA pin D7B D6B AL MST TRX Accessed to SBIDBR or SBICRB INTSBI Figure 2.12.10 Example of when a Serial Bus Interface Circuit ...
Page 117
Data Transfer Bus (1) Device initialization For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”. Specify the data length to 8 bits to count clocks for an acknowledge ...
Page 118
Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine whether the mode is a master or slave. a. When the MST is “1” (Master mode) Check the TRX ...
Page 119
To make the transmitter terminate transmit, clear the ACK to “0” before reading data which is 1-word before the last data to be received. A serial bus interface circuit does not generate a clock pulse for the acknowledge signal by ...
Page 120
Check the AL (Bit3 in the SBISR), the TRX (Bit6 in the SBISR), the AAS (Bit2 in the SBISR), and the AD0 (Bit1 in the SBISR) and implements processes according to conditions listed in Table 2.12.4. Table 2.12.4 Operation in ...
Page 121
Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart a serial bus interface circuit. Clear “0” to the MST, TRX ...
Page 122
SIO (Synchronous Serial Interface) The TMP86FM48 contains two channels of SIO (Synchronous serial interface). These serial interfaces connect to an external device via SI1, SI2, SO1, SO2, SI2, SO1, SO2, and SCK1 P12. When these pins are used as ...
Page 123
Control The SIO is controlled using the serial interface control register (SIO1CR). The operating status of the serial interface can be inspected by reading the status register (SIO1SR). Serial Interface Control Register SIO1CR SIOS ...
Page 124
Serial Interface Status Register SIO1SR SIOF SEF TXF RXF (0018H) Serial transfer operation SIOF status monitor SEF Number of clocks monitor TXF Transmit buffer empty flag RXF Receive buffer full flag TXERR Transfer operation error flag ...
Page 125
Functional Description (1) Serial clock a. Clock source The serial clock can be selected by using SIO1CR<SCK>. When the serial clock is changed, the writing instruction to SIO1CR<SCK> should be executed while the transfer is stopped (when SIO1SR<SIOF> = ...
Page 126
External clock When an external clock is selected by setting SIO1CR<SCK> to “111”, the clock via the SCK1 To ensure shift operation, the serial clock pulse width must be 4/fc or more for both “H” and “L” levels. pin ...
Page 127
Transfer bit direction Transfer data direction can be selected by using SIO1CR<SIODIR>. The transfer data direction can’t be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIO1CR<SIODIR> should be executed ...
Page 128
LSB transmit/receive mode LSB transmit/receive mode are selected by setting SIO1CR<SIODIR> to “1”, in which case the data is transferred sequentially beginning with the least significant bit (Bit0) and the data is received sequentially beginning with the least significant ...
Page 129
Transfer modes Transmit, receive and transmit/receive mode are selected by using SIO1CR<SIOM>. a. Transmit mode Transmit mode is selected by writing “00” to SIO1CR<SIOM>. 1. Starting the transmit operation Transmit mode is selected by setting “00” to SIO1CR<SIOM>. Serial ...
Page 130
Stopping the transmit operation There are two ways for stopping transmits operation. • The way of clearing SIO1CR<SIOS>. When SIO1CR<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the data is finished. When transmit operation ...
Page 131
SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin SCK1 input SO1 pin SIO1SR<TXF> INTSIO1 interrupt request A SIO1TDB Writing transmit Writing transmit data A data B ...
Page 132
Transmit error processing Transmit errors occur on the following situation. • Shift operation starts before writing next transmit data to SIO1TDB in external clock operation. If transmit errors occur during transmit operation, SIO1SR<TXERR> is set to “1” immediately after ...
Page 133
Receive mode The receive mode is selected by writing “01” to SIO1CR<SIOM>. 1. Starting the receive operation Receive mode is selected by setting “01” to SIO1CR<SIOM>. Serial clock is selected by using SIO1CR<SCK>. Transfer direction is selected by using ...
Page 134
SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin SCK1 output SI1 pin SIO1SR<RXF> INTSIO1 interrupt request SIO1RDB Figure 2.13.13 Example of Internal Clock and MSB Receive Mode SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> ...
Page 135
Receive error processing Receive errors occur on the following situation. To protect SIO1RDB and the shift SIO1SR<RXERR> is “1”. • Shift operation is finished before reading out received data from SIO1RDB at SIO1SR<RXF> is “1” external clock ...
Page 136
Transmit/receive mode The transmit/receive mode are selected by writing “10” to SIO1CR<SIOM>. 1. Starting the transmit/receive operation Transmit/receive mode is selected by writing “10” to SIO1CR<SIOM>. Serial clock is selected by using SIO1CR<SCK>. Transfer direction is selected by using ...
Page 137
In external clock operation, reading the received data from SIO1RDB and writing the next data to SIO1TDB must be finished before the shift operation of the next data begins. If the transmit data is not written to SIO1TDB after SIO1SR<TXF> ...
Page 138
Stopping the transmit/receive operation There are two ways for stopping the transmit/receive operation. • • SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin SCK1 output SO1 pin SI1 pin ...
Page 139
Writing transmit data SIO1CR<SIOS> SIO1SR<SIOF> Start shift operation SIO1SR<SEF> pin SCK1 input SO1 pin SI1 pin ...
Page 140
Transmit/receive error processing Transmit/receive errors occur on the following situation. Corrective action is different, which errors occur transmits or receives. Transmit errors Transmit errors occur on the following situation. • Shift operation starts before writing next transmit data to ...
Page 141
Receive errors Receive errors occur on the following situation. To protect SIO1RDB and the shift SIO1SR<RXERR> is “1”. • Shift operation is finished before reading out received data from SIO1RDB at SIO1SR<RXF> is “1” external clock operation. If ...
Page 142
SCK1 SIO1SR<SIOF> SO1 pin Figure 2.13.20 Hold Time of the End of Transmit/Receive Mode 86FM48-138 TMP86FM48 T SODH 4/fc ≤ T SODH ≤ 8/fc 2007-08-24 ...
Page 143
Key-On Wake-Up (KWU) In the TMP86FM48, the STOP mode must be released by not only P20 ( also P64 to P67 pins. When the STOP mode is released by P64 to P67 pins, the P20 ( used. 2.14.1 Configuration ...
Page 144
Control P64 to P67 (STOP0 to STOP3) pin can controlled by key-on wake-up control register (STOPCR). It can be configured as enable/disable in 1-bit unit. STOP mode can be entered by setting up the system control register1 (SYSCR1), and ...
Page 145
AD Converter (ADC) The TMP86FM48 has a 10-bit successive approximation type AD converter. 2.15.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 2.15.1. It consists of control registers ADCCR1 and ADCCR2, registers ADCDR1 ...
Page 146
Register Configuration The AD converter consists of the following four registers: • AD converter control register 1 (ADCCR1) • AD converter control register 2 (ADCCR2) • AD conversion result register 1/2 (ADCDR1/ADCDR2) (1) AD converter control register 1 (ADCCR1) ...
Page 147
AD Converter Control Register 1 ADCCR1 (000E ) ADRS AMD H ADRS AD conversion start AMD AD operating mode AINDS Analog input control SAIN Analog input channel select Note 1: Select analog input when AD converter stops ...
Page 148
AD Conversion Result Register ADCDR1 (0027 ) AD09 AD08 AD07 H ADCDR2 (0026 ) AD01 AD00 EOCF H EOCF AD conversion end flag ADBF AD conversion busy flag Note 1: The EOCF is cleared ...
Page 149
AD Converter Operation Modes There are following two AD converter operation modes: • Software start: AD conversion is performed once by setting AMD to “01B” and • Repeat mode: (1) Software start mode After setting ADCCR1<AMD> to “01” (Software ...
Page 150
Example: After selecting the conversion time of 39.0 µ MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, read the converted value, store the lower 2 bits in address 009EH and store ...
Page 151
STOP and SLOW Modes during AD Conversion When the STOP or SLOW mode is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value). ...
Page 152
... The internal equivalent circuit of the analog input pins is shown in Figure 2.15.7. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capacitor external to the chip. Allowable signal source impedance 5 kΩ ...
Page 153
FLASH Memory 2.16.1 Outline The TMP86FM48 incorporates 32768 bytes of FLASH memory (Address 8000H to FFFFH). Of these bytes, 512 bytes (Address 8000H to 81FFH) can be used as data memory. When these 512 bytes (Address 8000H to 81FFH) ...
Page 154
Differences among Product Series The specifications of the FLASH product (TMP86FM48) are different from those of the emulation chip (TMP86C948) as listed below. See 2.17.2 “Control ” for explanations about the control registers. Rewriting the EEPCR register<EEPMD, EEPRS, MNPWDW> ...
Page 155
FLASH Memory Configuration 64 consecutive bytes in the FLASH area are treated as one group, which is defined as a page. The TMP86FM48 incorporates a one-page temporary data buffer. Writing data to FLASH is temporarily stored in this 64-byte ...
Page 156
Data Memory of FLASH(address 8000H to 81FFH) The TMP86FM48 incorporates 512 bytes (8000H to 81FFH) of data memory of FLASH, which features: • In the MCU mode, user-created programs can rewrite the data memory of FLASH in page (64 ...
Page 157
Control The FLASH is controlled by FLASH control register (EEPCR), FLASH status register (EEPSR) and FLASH write emulate time control register (EEPEVA). FLASH Control Register EEPCR EEPMD (1FE0H) FLASH write enable control EEPMD (Write protect) EEPRS ...
Page 158
FLASH status register 7 6 EEPSR (1FE1H) Interrupt detection during a write to WINT the FLASH FLASH control EWUPEN circuit status monitor BFBUSY FLASH write busy flag Note nonmaskable interrupt occurs during a write to the FLASH, ...
Page 159
FLASH Write Emulation Time Control Register (Setting of this register functions only in emulation chip (TMP86C948).) 7 6 EEPEVA (1FE2H) Controlling the FLASH write EEPSUCR emulation time [s] for emulation chip Note 1: Only in the emulation chip, the EEPSUCR ...
Page 160
FLASH Write Enable Control (EEPCR<EEPMD>) In the FLASH product, the control register can be used to disable a write to the FLASH (Write protect) in order to prevent a write to the FLASH from occurring by mistake because of ...
Page 161
FLASH Write Forcible Stop (EEPCR<EEPRS>) To forcibly stop a write to the FLASH, set the EEPCR<EEPRS> to “1”. Setting the EEPCR<EEPRS> to “1” initializes the write data counter of data buffer and forcibly stops a write, and then a ...
Page 162
Buffer 0 Data 0 ? Buffer 1 ? Buffer 2 ? Buffer 63 ? Write to the EPCR<EEPRS> = “1” EEPCR<EEPRS> Write instruction to the FLASH area Write data counter 0 1 EEPSR<BFBUSY> EEPSR<EWUPEN> FLASH warm-up 0 counter FLASH control ...
Page 163
Power Control for the FLASH Control Circuit For the FLASH product possible to turn off the power for FLASH control circuit (such as a regulator) to suppress power consumption if the FLASH area is not accessed. For ...
Page 164
If the EEPCR<MNPWDW> is “1”, entering a STOP mode forcibly turns off the power for the FLASH control circuit. When the STOP mode is released, a STOP mode oscillation warm-up is carried out, and then the CPU wait period (Warm-up ...
Page 165
Example: Performing software-based power control for the FLASH control circuit sRAMAREA (WDTCR2),4Eh CLR (EEPCR).0 SET (EEPCR).0 sLOOP1: TEST (EEPSR).1 JRS T,sLOOP1 JP MAIN 86FM48-161 TMP86FM48 Disable an interrupt (IMF ← “0” Clear the binary counter if ...
Page 166
Automatic Power Control for the FLASH Control Circuit (EEPCR<ATPWDW>) The EEPCR<ATPWDW> automatic power control bit for the FLASH control circuit possible to suppress power consumption by automatically shutting down the power for the FLASH control ...
Page 167
Accessing the FLASH Data Memory Area During the writing to the data memory of FLASH area, neither a read nor fetch can be performed for the 8000H to FFFFH area. Therefore, to write the data memory of FLASH, the ...
Page 168
Method of Developing the Control Program in the RAM Area To develop the program in RAM, the write control program should be stored in FLASH beforehand or should load from external device by using peripheral function (Example: UART, SIO ...
Page 169
Method of specifying an address for a write to the FLASH The FLASH page to be written is specified by the 10 high-order bits of the address of the first-byte data. The first-byte data is stored at the first ...
Page 170
Buffer 0 ? Data 0 Buffer 1 ? Buffer 2 ? Buffer 63 ? FLASH cell Write instruction to the FLASH area Write data counter 1 0 EEPSR<BFBUSY> EEPSR<EWUPEN> Figure 2.17.10 Write to the FLASH Data Memory Area (In case ...
Page 171
Method of Using Support Programs in the BOOT-ROM The BOOT-ROM of TMP86FM48 has Support Program to simplify writing/reading of FLASH. This program supports three subroutines. 1. Writing to data FLASH from RAM 2. Reading from data FLASH to RAM ...
Page 172
Note 1: Steps above are executed in the FLASH area. Note 2: Support program 1 rewrites the HL, DE, B, and WA registers. If the existing data in them are necessary, save it in advance. Note 3: ...
Page 173
Example) Setting 0050H 8100H, and B = 1FH, and executing a CALL instruction for support program 2 (3E2CH) 0050H 0051H 0052H Block transfer 0053H 008FH Figure 2.17.13 Example of Using Support Program 2 to Read ...
Page 174
Support program 2 (Block transfer from the FLASH area to the RAM area) Shown below is the support program source code for reading data from the FLASH. USER_SUB_READ section code abs = 3E2CH sUSER_main2: AND DE,0FFC0 LD (EEPCR),0CBH sEEP_read_loop: ...
Page 175
FLASH Program Memory The TMP86FM48 incorporates 32256 bytes (8200H to FFFFH) of program memory. If the data memory of FLASH is not in use, the TMP86FM48 can be used as an FLASH product with 32768 full bytes. To write ...
Page 176
Serial PROM Mode 2.19.1 Outline The TMP86FM48 has a 2 Kbytes BOOT-ROM for programming to FLASH memory. This BOOT-ROM is a mask ROM that contains a program to write the FLASH memory on-board. The BOOT-ROM is available in a ...
Page 177
Pin Function In the serial PROM mode, TXD (P06) and RXD (P05) pins are used as a serial interface pin. Pin Name Input/ (Serial PROM Mode) Output TXD Output RXD Input BOOT Input RESET Input TEST Input VDD, AVDD ...
Page 178
Activating Serial PROM Mode The following is a procedure of setting of serial PROM mode. Figure 2.19.3 shows a serial PROM mode timing. (1) Turn on the power to the VDD pin. (2) Set the RESET (3) Set the ...
Page 179
Table 2.19.4 Operating Frequency and Baud Rate in Serial PROM Mode Reference Baud Rate 76800 (bps) Baud Rate 04H Modification Data (Note 3) Ref. Baud Area Frequency rate (MHz) (MHz) (bps) − 1.91~2.10 − 4 3.82~4.19 2 − ...
Page 180
Operation Mode There are four operating modes in serial PROM mode: FLASH memory writing mode, RAM loader mode, FLASH memory SUM output mode and Product discrimination code output mode. For details about these modes, refer to “(1) FLASH memory ...
Page 181
FLASH Writing Mode (Operation command: 30H) Table 2.19.6 shows FLASH memory writing mode process. Table 2.19.6 FLASH Writing Mode Process Number of Bytes Transfer Data from External Transferred Controller to TMP86FM48 BOOT 1st byte Matching data (5Ah) − ROM ...
Page 182
Description of FLASH memory writing mode 1. The receive data in the 1st byte is the matching data. When the boot program starts in serial PROM mode, TMP86FM48 (Mentioned as “device” hereafter) waits for the matching data (5AH) to receive. ...
Page 183
The 15th through the m’th bytes are the password data. The number of passwords is the data (N) indicated by the password count storage address. The password data are compared for N entries beginning with the password comparison start ...
Page 184
RAM Loader Mode (Operation Command: 60H) Table 2.19.7 shows RAM loader mode process. Table 2.19.7 RAM Loader Mode Process Number of Bytes Transfer Data from External Transferred Controller to TMP86FM48 BOOT 1st byte Matching data (5AH) − ROM 2nd ...
Page 185
TMP86FM48 should be reset by Note 6: Do not send only end record after transferring of password string. If the TMP86FM48 receives the end record only after reception of password string, it does not operate correctly. Note 7: ...
Page 186
FLASH Memory SUM Output Mode (Operation Command: 90H) Table 2.19.8 shows FLASH memory SUM output mode process. Table 2.19.8 FLASH Memory SUM Output Process Number of Bytes Transfer Data from External Transferred Controller to TMP86FM48 BOOT 1st byte Matching ...
Page 187
Product Discrimination Code Output Mode (Operation Command: C0H) Table 2.19.9 shows product discrimination code output mode process. Table 2.19.9 Product Discrimination Code Output Process Number of Bytes Transfer Data from External Transferred Controller to TMP86FM48 BOOT 1st byte Matching ...
Page 188
FLASH memory Writing Data Format FLASH area of TMP86FM48 consists of 512 pages and one page size is 64 bytes. Writing to FLASH is executed by page writing. Therefore necessary to send 64 bytes data (for one ...
Page 189
Error Code When the device detects an error, the error codes are sent to the controller. Transmit Data 62H, 62H, 62H 63H, 63H, 63H A1H, A1H, A1H A3H, A3H, A3H Note1: If password error occurs, the TMP86FM48 doesn’t send ...
Page 190
Intel Hex Format (Binary) 1. After receiving the checksum of a record, the device waits for the start mark data (3AH for “:”) of the next record. Therefore, the device ignores the data, which does not match the start ...
Page 191
Table 2.19.12 Password Setting in the Blank Product and Non Blank Product Password PNSA (Password count storage addresses) PCSA (Password comparison start address) N (Password count) Setting of password Note 1: When all data of addresses from FFE0H to FFFFH ...
Page 192
Password String A string of passwords in the received data are compared with the data in the FLASH memory. In the following cases, a password error occurs: • When the received data does not match the data in the ...
Page 193
Product Discrimination Code The product discrimination code is a 13-byte data, that includes the start address and the end address of ROM. Table 2.19.13 shows the product discrimination code format. Table 2.19.13 Product Discrimination Code Format Data The Meaning ...
Page 194
Flowchart START Setup UART data receive Receive data = “5AH” Change baud rate (Adjust to 9600 baud Yes UART data transmit (Transmit data = “5AH”) UART data receive UART data transmit (Echoed back the baud rate modification data) Change ...
Page 195
UART Timing Table 2.19.14 UART Timing-1 (VDD = 2 3 MHz to 16 MHz 25°C) Parameter Time from the reception of a matching data until the output of an echo back ...
Page 196
Input/Output Circuitry (1) Control pins The input/output circuitries of the TMP86FM48 control pins are shown below. Control Pin I/O XIN Input XOUT Output NORMAL1 mode XTIN Input XTOUT Output Refer to port P2 RESET Input Address-trap-reset Watchdog-timer System-clock-reset TEST Input ...
Page 197
Input/output ports Port I/O Initial “High-Z” Pch control (Control output) Data output P0 I/O Input from output latch P1 Disable Pin input (Control input) Initial “High-Z” Pch control Data output P20 I/O Input from output latch Disable Pin input ...
Page 198
Port I/O Initial “High-Z” Data output Input from output latch P6 I/O control I/O P7 Input control Pin input Disable Analog input Initial “High-Z” Data output Input from output latch P8 I/O I/O control Pin input Disable Input/Output Circuitry VDD ...
Page 199
Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Supply voltage Input voltage Output voltage Output current (Per 1 pin) Output current (Total) Power dissipation [Topr = 85°C] Soldering temperature (Time) Storage temperature Operating temperature Note: The absolute maximum ratings are rated ...
Page 200
Recommended Operating Condition-1 (MCU mode) Parameter Symbol Pins Supply voltage Except Hysteresis input IH1 Input high level V Hysteresis input IH2 V IH3 V Except Hysteresis input IL1 Input low level V Hysteresis input IL2 V IL3 ...