TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 113

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(4) Slave address and address recognition mode specification
(5) Master/slave selection
(6) Transmitter/receiver selection
Mode
Master
Slave
mode
mode
the slave address, clear the ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits7 to 1 in
I2CAR) to the slave address.
the slave address, set the ALS to “1”. With a free data format, the slave address and the
direction bit are not recognized, and they are processed as data from immediately after
start condition.
device, the MST should be cleared to “0”.
cleared to “0” by the hardware.
set the device as a receiver, the TRX should be cleared to “0”. When data with an
addressing format is transferred in the slave mode, the TRX is set to “1” by a hardware
if the direction bit (R/
hardware if the bit is “0”. In the master mode, after an acknowledge signal is returned
from the slave device, the TRX is cleared to “0” by a hardware if a transmitted direction
bit is “1”, and is set to “1” by a hardware if it is “0”. When an acknowledge signal is not
returned, the current condition is maintained.
cleared to “0” by the hardware. Table 2.12.2 shows TRX changing conditions in each
mode and TRX value after changing.
and a direction bit are not recognized. They are handled as data just after generating a
start condition. The TRX is not changed by a hardware.
When the serial bus interface circuit is used with an addressing format to recognize
When the serial bus interface circuit is used with a free data format not to recognize
To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave
When a stop condition on the bus or an arbitration lost is detected, the MST is
To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to “1”. To
When a stop condition on the bus or an arbitration lost is detected, the TRX is
When a serial bus interface circuit operates in the free data format, a slave address
down the SCL pin to the low level.
high-level period and the master device with the longest low-level period from
among those master devices connected to the bus.
The clock pulse on the bus is determined by the master device with the shortest
Table 2.12.2 TRX changing conditions in each mode
Direction Bit
“0”
“1”
“0”
“1”
W
) sent from the master device is “1”, and is cleared to “0” by a
86FM48-109
A received slave address is the
same value set to I2CAR
ACK signal is returned
Conditions
TRX after Changing
“0”
“1”
“1”
“0”
TMP86FM48
2007-08-24