TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 20

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

System Control Register 1
SYSCR1
(0038
System Control Register 2
SYSCR2
(0039
H
H
)
)
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when
Note 2: When STOP mode is released with
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may
Note 6: When the key-on wake-up input (STOP0 to STOP3) is used, RELM should be set to “1”.
Note 7: Port P20 is used as
Note 8: When the STOP mode is started with the EEPCR<MNPWDW> = “1”, the CPU wait period for stabilizing of
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or
Note 2: *: Don’t care, TG: Timing generator
Note 3: Bits 3, 1and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch
STOP
TGHALT
XEN
OUTEN
SYSCK
RELM
RETM
XTEN
STOP
IDLE
7
WUT
7
XEN
transiting from SLOW mode to STOP mode.
RETM contents.
cause interrupt request on account of falling edge.
P20 becomes High-Z mode.
the power supply of Flash control circuit is executed after in the STOP warm-up time.
(The CPU wait period for FLASH is shown in parentheses)
XTEN is cleared to “0” when SYSCK = “1”.
clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
of peripherals may be set after IDLE0 or SLEEP0 mode is released.
RELM
XTEN
High-frequency oscillator control
Low-frequency oscillator control
Main system clock select (write)/main
system clock monitor (read)
CPU and watchdog timer control
(IDLE1/2, SLEEP1/2 mode)
TG control
(IDLE0, SLEEP0 mode)
STOP mode start
Release method for STOP pin
(P20)
Operating mode after STOP
mode
Port output during STOP
mode
Warm-up time at releasing
STOP mode (Note 8)
6
6
SYSCK
RETM
5
5
Figure 1.4.7 System Control Registers
OUTEN
STOP
IDLE
4
4
pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and
3
3
86FM48-16
WUT
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
0: Edge-sensitive release
1: Level-sensitive release
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
0: High impedance
1: Output kept
RESET
00
01
10
11
TGHALT
2
2
Return to NORMAL mode
0: Turn off oscillation
1: Turn on oscillation
0: Turn off oscillation
1: Turn on oscillation
0: High-frequency clock
1: Low-frequency clock
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from
pin input, a return is made to NORMAL1 regardless of the
(start IDLE1/2, SLEEP1/2 mode)
TG. (Start IDLE0, SLEEP0 mode)
3 × 2
3 × 2
1
1
2
2
16
16
14
14
/fc
/fc
/fc
/fc
+ (2
+ (2
+ (2
+ (2
0
0
10
10
10
10
/fc)
/fc)
/fc)
/fc)
(Initial value: 0000 00**)
(Initial value: 1000 *0**)
Return to SLOW mode
3 × 2
3 × 2
2
2
13
13
6
6
/fs
/fs
/fs
/fs
+ (2
+ (2
+ (2
+ (2
3
3
3
3
TMP86FM48
/fs)
/fs)
/fs)
/fs)
2007-08-24
R/W
R/W