TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 163

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.17.5
2.17.5.1 Software-based Power Control for the FLASH Control Circuit (EEPCR<MNPWDW>)
Power Control for the FLASH Control Circuit
(such as a regulator) to suppress power consumption if the FLASH area is not accessed. For
the emulation chip (TMP86C948), the register setting and the CPU wait functions behave
in the same manner as for the FLASH product to maintain compatibility; however, power
consumption is not suppressed.
FLASH control circuit. If the power for the FLASH control circuit is turned off according to
the setting of these registers, starting to use the circuits again needs to allow warm-up time
for the power supply.
(64 µs @16 MHz)
IDLE0/1/2 Mode
NORMAL1/2
For the FLASH product, it is possible to turn off the power for FLASH control circuit
The EEPCR<MNPWDW> and EEPCR<ATPWDW> are used to control the power for the
Table 2.17.1 Power Supply Warm-up Time (CPU wait) for the FLASH Control Circuit
2
10
control circuit. When a program is being executed in the RAM area, setting this bit
enables software-based power control. Clearing the EEPCR<MNPWDW> to “0”
immediately turns off the power for the FLASH control circuit. Once the
EEPCR<MNPWDW> is switched from “0” to “1”, before attempting a read or fetch
from the FLASH area, it is necessary to insert a warm up period by software until the
power supply is stabilized. In this case, because the CPU wait is not executed, any
other instructions except accessing to Flash (write or read) are available. When
MNPWDW is changed from “0” to “1”, EWUPEN becomes “1” after taking 2
(SYSCK = “0”) or 2
performed until the EEPSR<EWUPEN> becomes “1”. An example of setting is given
below.
(1) Example of controlling the EEPCR<MNPWDW>
/fc [s]
The EEPCR<MNPWDW> is a software-based power control bit for the FLASH
This procedure enables the FLASH area to be accessed.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Transfer a program for controlling the EEPCR<MNPWDW> to the RAM area.
Release an address trap in the RAM area (Setup the WDTCR1 and WDTCR2
registers).
Jump to the control program transferred to the RAM area.
Clear the interrupt master enable flag (IMF ← “0”).
Clear the binary counter if the watchdog timer is in use.
To turn off the power for the FLASH control circuit, clear the
EEPCR<MNPWDW> to “0”.
Perform CPU processing as required.
To access the FLASH area again, set the EEPCR<MNPWDW> to “1”.
Keep program polling until the EEPSR<EWUPEN> becomes “1”.
(Upon completion of an FLASH warming-up, the EEPSR<EWUPEN> is set to
“1”. It takes 2
becomes “1”.)
(244 µs @32.768 kHz)
SLEEP0/1/2 Mode
SLOW1/2
2
3
/fs [s]
3
/fs [s] (SYSCK = “1”). Usually software-based polling should be
10
/fc (SYSCK = “0”) or 2
86FM48-159
STOP warm-up time + 2
To Return to a NORMAL Mode
STOP Mode (when EEPCR<MNPWDW> = “1”)
3
/fs (SYSCK = “1”) until EWUPEN
10
/fc [s]
STOP warm-up time + 2
To Return to a SLOW Mode
TMP86FM48
2007-08-24
10
3
/fs [s]
/fc [s]