TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 67

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Watchdog Timer Register 1
Watchdog Timer Register 2
WDTCR2
WDTCR1
(0034
(0035
H
H
)
)
Note 1: WDTOUT cannot be set to “1” by program after clearing WDTOUT to “0”.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions.
Note 4: The watchdog timer must be disabled or the counter must be cleared immediately before entering to the
Note 5: To disable the watchdog timer, always write “4E
Note 1: The disable code is invalid unless written when WDTCR1<WDTEN> = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write clear code 4E
WDTCR2
WDTOUT
(2) Watchdog timer enable
(3) Watchdog timer disable
WDTEN
WDTT
7
7
immediately after reset is released.
binary counter before writing “0” to WDTCR1<WDTEN>, and then write “B1
(Disable code) to WDTCR2. The watchdog timer is not disabled if this procedure is
reversed and the disable code is written to WDTCR2 before WDTCR1<WDTEN> is
cleared to “0”. Also, immediately before these procedure, disable the interrupt master
flag (IMF) by DI instruction. During disabling the watchdog timer, the binary counters
are cleared to “0”.
STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing
the STOP mode.
before writing “0” to WDTEN, and then write “B1
Also, immediately before these procedure, disable the interrupt mater flag (IMF) by DI instruction.
The watchdog timer is enabled by setting WDTCR1<WDTEN> to “1”.
WDTCR1<WDTEN> is initialized to “1” during reset, so the watchdog timer operates
To disable the watchdog time, write “4E
Watchdog timer control
code write register
Watchdog timer
enable/disable
Watchdog timer
detection time [s]
Watchdog timer
output select
6
6
(ATAS) (ATOUT) WDTEN
Figure 2.4.2 Watchdog Timer Control Registers
5
5
H
within 3/4 of the time set in WDTCR1<WDTT>.
4
4
3
3
0: Disable (It is necessary to write the disable code to WDTCR2)
1: Enable
0: Interrupt request
1: Reset request
86FM48-63
4E
B1
D2
Others: Invalid
H
H
H
:
:
:
00
01
10
11
2
2
Watchdog timer binary counter clear (Clear code)
Watchdog timer disable (Disable code)
Enable assigning address trap area
WDTT
H
H
” (Clear code) to WDTCR2 for clearing the binary counter
” (Disable code) to WDTCR2.
1
1
H
DV7CK = 0
” (Clear code) to WDTCR2 for clearing the
2
2
2
2
NORMAL1/2 mode
25
23
21
19
WDTOUT
/fc
/fc
/fc
/fc
0
0
(Initial value: **11 1001)
(Initial value: **** ****)
DV7CK = 1
2
2
2
2
17
15
13
11
/fs
/fs
/fs
/fs
SLOW
mode
2
2
2
2
17
15
13
11
/fs
/fs
/fs
/fs
TMP86FM48
2007-08-24
Write
Write
only
only
H
”