TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 23

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

STOP pin
XOUT pin
NORMAL operation
STOP mode started
by the program.
Note: When the STOP mode is started with the EEPCR<MNPWDW> = “1”, the CPU wait for stabilizing of the power
supply of Flash control circuit is executed after in the STOP warm-up time.
STOP mode is released by the following sequence.
Note 1: When the STOP mode is released, the start is made after the prescaler and
Note 2: STOP mode can also be released by inputting low level on the
Note 3: When STOP mode is released with a low hold voltage, the following
a.
b.
c.
d.
In the dual-clock mode, when returning to NORMAL2, both the
high-frequency and low-frequency clock oscillators are turned on; when
returning to SLOW1 mode, only the low-frequency clock oscillator is turned
on. In the single-clock mode, only the high-frequency clock oscillator is
turned on.
When the EEPCR<MNPWDW> is “0”, normal operation resumes with the
instruction following the STOP mode start instruction after the STOP
Warm-up.
A STOP warm-up period is inserted to allow oscillation time to stabilize.
During STOP warm-up, all internal operations remain halted. Four
different STOP warm-up times can be selected with the SYSCR1<WUT> in
accordance with the resonator characteristics.
When the EEPCR<MNPWDW> is “1”, the CPU wait period is inserted to
stabilize the power supply of Flash control circuit. During CPU wait,
though CPU operations remain halted, the peripheral function operation is
resumed, and the counting of the timing generator is restarted. After the
CPU wait is finished, normal operation resumes with the instruction
following the STOP mode start instruction.
Figure 1.4.9 Edge-sensitive Release Mode
the divider of the timing generator are cleared to “0”.
which immediately performs the normal reset operation.
cautions must be observed.
The power supply voltage must be at the operating voltage level before
releasing STOP mode. The
together with the power supply voltage. In this case, if an external time
constant circuit has been connected, the
increase at a slower pace than the power supply voltage. At this time, there
is a danger that a reset may occur if input voltage level of the
drops below the non-inverting high-level input voltage (Hysteresis input).
STOP operation
86FM48-19
V
IH
Warm-up
STOP
STOP mode is released by the hardware at the rising edge
of
STOP
RESET
CPU wait
period
pin input.
pin input must also be “H” level, rising
Only when EEPCR<MNPWDW> is “1”.
(The CPU wait period is added.)
NORMAL
operation
RESET
STOP operation
pin input voltage will
TMP86FM48
2007-08-24
RESET
RESET
pin,
pin