TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 73

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

TC1CK
Table 2.7.1 Source Clock (internal clock) for Timer/Counter 1 (Example: at fc = 16 MHz, fs = 32.768kHz)
00
01
10
2.7.3
Note 10: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting
Note :
Resolution
Function
window, pulse width measurement, programmable pulse generator output mode.
(1) Timer mode
128
Timer/counter 1 has six operating modes: timer, external trigger timer, event counter,
[µs]
8.0
0.5
TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1
interrupt is generated, and the counter is cleared to “0”. Counting up resumes after the
counter is cleared. The current contents of up counter can be transferred to TC1DRB
by setting TC1CR<ACAP1> to “1” (Auto capture function). Use the auto-capture
function in the operative condition of TC1. A captured value may not be fixed if it's read
after the execution of the timer stop or auto-capture disable. Read the capture value in
a capture enabled condition. Since the up-counter value is captured into TC1DRB by
the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read
the captured value, wait at least one cycle of the internal source clock before reading
TC1DRB for the first time.
TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source
clock before reading TC1DRB for the first time.
Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting
TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source
clock before reading TC1DRB for the first time.
In this mode, counting up is performed using the internal clock. The contents of
DV7CK = 0
Example 1: Sets the timer mode with source clock fc/2
Example 2: Auto-capture
Figure 2.7.2 Timer Registers and TC1 Control Register
Time Setting
NORMAL1/2, IDLE1/2 Mode
Maximum
32.77 m
8.39
0.524
[s]
(at fc = 16 MHz, DV7CK = 0)
LDW
DI
SET
EI
LD
LD
LD
LD
Resolution
(TC1DRA), 1E84H
(EIRL). 5
(TC1CR), 00000000B
(TC1CR), 00010000B
(TC1CR), 01010000B
86FM48-69
WA, (TC1DRB)
244.14
[µs]
8.0
0.5
DV7CK = 1
Time Setting
Maximum
16.0
32.77 m
0.524
[s]
11
[Hz] and generates an interrupt 1 second later
;
;
;
;
;
;
;
;
Sets the timer register
(1 s ÷ 2
IMF = “0”
Enable INTTC1
IMF = “1”
TFF1 ← “0”, TC1CK ← “00”, TC1M ← “00”
Starts TC1
ACAP1 ← “1” (Capture)
Reads the capture value
SLOW1/2, SLEEP1/2 Mode
Resolution
11
244.14
/fc = 1E84H)
[µs]
−
−
Time Setting
TMP86FM48
Maximum
2007-08-24
16.0
[s]
−
−