TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 126

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

SIO1CR<SIOS>
Shift register
SO1 pin
SIO1CR<SIOS>
SI1 pin
Shift register
SCK1
SCK1
pin
pin
2.
b.
01234567
When an external clock is selected by setting SIO1CR<SCK> to “111”, the clock
via the
To ensure shift operation, the serial clock pulse width must be 4/fc or more for both
“H” and “L” levels.
The leading edge is used to transmit data, and the trailing edge is used to receive
data.
1.
2.
External clock
Shift edges
SCK1
*********
Data is shifted on leading edges of the serial clock (Falling edges of the
pin input/output).
Data is shifted on trailing edges of the serial clock (Rising edges of the
pin input/output).
Leading edge shift
Trailing edge shift
pin
*0123456 **012345 ***01234 ****0123 *****012 ******01 *******0 *********
SCK1
Shift out
Bit7
Bit7
7******* 67****** 567***** 4567**** 34567*** 234567** 1234567* 01234567
pin from an external source is used as the serial clock.
Figure 2.13.6 External Clock
Figure 2.13.7 Shift Edge
Bit6
Bit6
86FM48-122
T
(a) Leading edge shift (Example of MSB transfer)
(b) Trailing edge shift (Example of MSB transfer)
SCKL
Bit5
Bit5
VIL
Bit4
Bit4
VIH
T
SCKH
Bit3
Bit3
Bit2
Bit2
T
SCKL
, T
Bit1
Bit1
SCKH
≥ 4/fc
TMP86FM48
2007-08-24
Bit0
Bit0
SCK1
SCK1