TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 120

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

TRX
Note: In the slave mode, if the slave address set in I2CAR is “00000000B”, the TRX changes to “1” by
1
0
AL
receiving the start byte data “00000001B”.
1
0
1
0
(4) Stop condition generation
AAS
1
1
0
1
0
1
0
to the MST, TRX and PIN, and clear “0” to the BB. Do not modify the contents of the
MST, TRX, BB, PIN until a stop condition is generated on a bus.
circuit generates a stop condition after they release a SCL line.
When the BB is “1”, a sequence of generating a stop condition is started by setting “1”
When a SCL line on a bus is pulled-down by other devices, a serial bus interface
in the SBISR), and the AD0 (Bit1 in the SBISR) and implements processes
according to conditions listed in Table 2.12.4.
AD0
“1” → MST
“1” → TRX
“0” → BB
“1” → PIN
SCL pin
SDA pin
PIN
BB (Read)
1/0
1/0
1/0
Check the AL (Bit3 in the SBISR), the TRX (Bit6 in the SBISR), the AAS (Bit2
0
0
0
0
when transmitting a slave address. And
receives a slave address of which the value
of the direction bit sent from another master
is “1”.
interface circuit receives a slave address of
which the value of the direction bit sent from
the master is “1”.
In the slave transmitter mode, 1-word data is
transmitted.
when transmitting a slave address. And
receives a slave address of which the value
of the direction bit sent from another master
is “0” or receives a “GENERAL CALL”.
when transmitting a slave address or data.
And terminates transferring word data.
interface circuit receives a slave address of
which the value of the direction bit sent from
the master is “0” or receives “GENERAL
CALL”.
interface circuit terminates receiving of
1-word data.
A serial bus interface circuit loses arbitration
In the slave receiver mode, a serial bus
A serial bus interface circuit loses arbitration
A serial bus interface circuit loses arbitration
In the slave receiver mode, a serial bus
In the slave receiver mode, a serial bus
Figure 2.12.15 Stop Condition Generation
Table 2.12.4 Operation in the Slave Mode
Conditions
86FM48-116
Stop condition
Set the number of bits in 1 word to the BC
and write transmitted data to the SBIDBR.
Test the LRB. If the LRB is set to “1”, set the
PIN to “1” since the receiver does not
request next data. Then, clear the TRX to “0”
to release the bus. If the LRB is set to “0”, set
the number of bits in 1 word to the BC and
write transmitted data to the SBIDBR since
the receiver requests next data.
Read the SBIDBR for setting the PIN to “1”
(Reading dummy data) or write “1” to the
PIN.
A serial bus interface circuit is changed to
slave mode. To clear AL to “0”, read the
SBIDBR or write the data to SBIDBR.
Read the SBIDBR for setting the PIN to “1”
(Reading dummy data) or write “1” to the
PIN.
Set the number of bits in 1-word to the BC
and read received data from the SBIDBR.
Process
TMP86FM48
2007-08-24