TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 54

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.2.3
Data input (P21PRD)
Data input (P22PRD)
Note: When XTEN<SYSCR2> is set to “1”, P21 and P22 become a high impedance state.
Data output (P21)
Data output (P22)
Port P2 (P22 to P20)
release signal input, and low-frequency crystal oscillator connection pins. It can be selected
whether output circuit of P2 port is CMOS (P21 and P22 have a pull-up resistor) output or a
sink open drain individually, by setting the output circuit control (P2OUTCR). When a
corresponding bit of P2OUTCR is cleared to “0”, the output circuit is selected to a sink open
drain and when a corresponding bit of P2OUTCR is set to “1”, the output circuit is selected
to a CMOS output. (In case of P21 and P22, the pull-up resistor is connected.)
(P2DR) should be set to “1”.
(XTOUT) in the dual-clock mode. In the single-clock mode, pins P21 and P22 can be used as
normal input/output ports.
mode release signal input, or an input port. If it is used as an output port, the interrupt
latch is set on the falling edge of the output pulse.
respective address. When read the output latch data, the P2DR should be read and when
read the terminal input data, the P2PRD register should be read.
to 3 are unstable.
P2OUTCR input
Data input (P21)
Data input (P22)
P2OUTCR input
Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode
When used as an input port or an external interrupt input, the respective output latch
During reset, the P2DR initialized to “1” and P2OUTCR is initialized to “0”.
A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22
It is recommended that pin P20 should be used as an external interrupt input, a STOP
P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their
If a read instruction is executed for port P2DR, P2OUTCR and P2PRD, read data of bits 7
P2OUTCR
P2OUTCR
OUTEN
STOP
XTEN
fs
Output latch
Output latch
D
D
D
D
Figure 2.2.4 Port 2 (P21 and P22)
Q
Q
Q
Q
86FM48-50
Osc.enable
VDD
VDD
P21 (XTIN)
P22 (XTOUT)
TMP86FM48
2007-08-24