TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 47

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Program counter
Stack pointer
General-purpose registers
Jump status flag
Zero flag
Carry flag
Half carry flag
Sign flag
Overflow flag
Interrupt master enable flag
Interrupt individual enable flags
Interrupt latches
1.6
RESET
1.6.1
Reset Circuit
address trap reset, a watchdog timer reset and a system clock reset. Table 1.6.1 shows on-chip
hardware initialization by reset action.
counter for stabilizing of the power supply for Flash, the reset period is 2
MHz).
system clock reset is not initialized when power is turned on, the reset operation occur for the
maximum 24/fc [s] (1.5 µs at 16.0 MHz).
On-chip Hardware
The TMP86FM48 has four types of reset generation procedures: an external reset input, an
Since the reset circuit has an 11-stage counter for generation of flash reset, which is the reset
Because the malfunction reset circuit such as watchdog timer reset, address trap reset and
Therefore, the maximum reset period is 24/fc [s] + 2
Table 1.6.1 shows on-chip hardware initialization by reset action.
External Reset Input
power supply voltage within the operating voltage range and oscillation stable, a reset is
applied and the internal state is initialized.
reset operation is released and the program execution starts at the vector address stored at
addresses FFFE
(W, A, B, C, D, E, H, L, IX, IY)
VDD
The
When the
When 2
RESET
10
/fc (65.5 µs at 16 MHz) period passes after the
Table 1.6.1 Initializing Internal Status by Reset Action
RESET
pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
H
to FFFF
Flash reset counter
(IMF)
(PC)
(SP)
(CF)
(HF)
(SF)
(VF)
(EF)
(ZF)
(JF)
(IL)
pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the
Malfunction reset
output circuit
Figure 1.6.1 Reset Circuit
H
Initial Value
.
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
(FFFE
86FM48-43
0
0
0
H
)
Reset input
Prescaler and Divider of timing
generator
Watchdog timer
Output latches of I/O ports
Control registers
RAM
On-chip Hardware
10
/fc [s] (65.5 µs at 16.0 MHz).
RESET
Watchdog timer reset
Adddress trap reset
System clock reset
pin input goes high, the
10
/fc [s] (64 µs at 16.0
Refer to I/O port
circuitry
Refer to each of
control register
Not initialized
Initial Value
TMP86FM48
Enable
2007-08-24
0