TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 36

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Internal/External (Reset)
1.5
Note 1: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to “0” (It is set for the
Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the
External
External
External
External
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Interrupt Control Circuit
internals. 4 of the internal sources are non-maskable interrupts, and the rest of them are
maskable interrupts.
independent vectors. The interrupt latch is set to “1” by the generation of its interrupt request
which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software
using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one
interrupts are generated simultaneously, interrupts are accepted in order which is dominated
by hardware. However, there are no prioritized interrupt factors among non-maskable
interrupts.
“Reset request” after reset is released). For details, see 2.4 Watchdog Timer.
“Reset request” after reset is released). For details, see 2.4.5 Address Trap.
The TMP86FM48 has a total (Reset is excluded) of 20 interrupt source: 5 externals and 15
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and
INTSWI
INTUNDEF (Executed the undefined instruction interrupt)
INTATRAP (Address trap interrupt)
INTWDT
INTTC1
INT1
INTTBT
INT2
INTTC3
INTSIO1
INTSIO2
INTTC5
INT3
INTADC
Reserved
Reserved
INTSBI
INTRXD
INTTXD
INTTC2
Reserved
Reserved
INT0
INT5
Interrupt Factors
(Software interrupt)
(Watchdog timer interrupt)
(External interrupt 0)
(TC1 interrupt)
(External interrupt 1)
(Time base timer interrupt)
(External interrupt 2)
(TC3 interrupt)
(Serial interface 1 interrupt)
(Serial interface 2 interrupt)
(TC5 interrupt)
(External interrupt 3)
(AD converter interrupt)
(Serial bus interface interrupt)
(UART received interrupt)
(UART transmitted interrupt)
(TC2 interrupt)
(External interrupt 5)
Table 1.5.1 Interrupt Sources
86FM48-32
Non-maskable
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
IMF•EF
Condition
Enable
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1
Interrupt
Latch
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
−
−
−
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2
3
4
5
6
7
8
9
Address
Vector
FFFE
FFFC
FFFC
FFFA
FFEE
FFEC
FFEA
FFBE
FFBC
FFBA
FFF8
FFF6
FFF4
FFF2
FFF0
FFE8
FFE6
FFE4
FFE2
FFE0
FFB8
FFB6
FFB4
FFB2
FFB0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
TMP86FM48
2007-08-24
High
Priority
15
16
17
18
19
20
21
22
23
24
10
11
12
13
14
1
2
2
2
2
5
6
7
8
9