TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 161

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.17.4
FLASH Write Forcible Stop (EEPCR<EEPRS>)
EEPCR<EEPRS> to “1” initializes the write data counter of data buffer and forcibly stops a
write, and then a warm-up (CPU wait) for the control circuit of Flash memory is executed.
After warm-up period, the EEPSR<BFBUSY> is cleared to “0”. The warm-up period is
2
data is stored as the first byte of the temporary data buffer and sets the EEPSR<BFBUSY>
to “1”. Therefore, it is necessary to write 64 bytes data to the temporary data buffer.
to “1” the specified page of FLASH is not written. (It keeps previous data.)
Note 1: After 64 bytes are written to the temporary data buffer, the setting the EEPCR<EEPRS>
Note 2: The EEPCR<EEPRS> can be rewritten only when a program is being executed in the
Note 3: During the warm-up period for Flash memory (CPU wait), the peripheral circuits
Note 4: When the EEPCR<EEPRS> is set to “1” with EEPSR<BFBUSY> = “0”, a warm-up is not
Note 5: If executed a write or read instruction to the Flash area immediately after setting
10
To forcibly stop a write to the FLASH, set the EEPCR<EEPRS> to “1”. Setting the
After 1 to 63 bytes are saved to the temporary data buffer, if the EEPCR<EEPRS> is set
/fc (SYSCK = “0”) or 2
Example: Reads the Flash memory data immediately after setting EEPCR<EEPRS> to “1”
to “1” may cause the writing the page of FLASH to an unexpected value.
RAM area. In the FLASH area, executing a write instruction to the EEPCR<EEPRS>
does not affect its setting.
continue operating, but the CPU stays at a halt until the warm-up is finished. Even if an
interrupt latch is set to “1” by generating of interrupt request, an interrupt sequence
doesn’t start till the end of warm-up. If interrupts occur during a warm-up period with IMF
= “1”, the interrupt sequence which depends on interrupt priority will start after warm-up
period.
executed.
EEPCR<EEPRS>, insert one or more machine cycle instructions after setting
EEPCR<EEPRS>.
LD
LD
NOP
LD
3
HL,8000H
(EEPCR),3FH
A,(HL)
/fs (SYSCK = “1”). After this, if writing to FLASH starts again,
86FM48-157
; Set EEPCR<EEPRS> to “1”
; NOP
; Reads the data of address 8000H
(Write or read instruction to the Flash memory)
(Do not execute write or read instruction immediately
after setting EEPCR<EEPRS>.)
TMP86FM48
2007-08-24