TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 16

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

1.4.3
Operation Mode Control Circuit
high-frequency and low-frequency clocks, and switches the main system clock. There are
two operating modes: single-clock and dual-clock. These modes are controlled by the system
control registers (SYSCR1 and SYSCR2).
system control registers.
(1) Single-clock mode
The operation mode control circuit starts and stops the oscillation circuits for the
Figure 1.4.6 shows the operating mode transition diagram and Figure 1.4.7 shows the
P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained
from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc
[s].
a.
b.
c.
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and
NORMAL1 mode
high-frequency clock.
watchdog timer are halted; however on-chip peripherals remain active (Operate
using the high-frequency clock).
NORMAL1 mode by an interrupt request from the on-chip peripherals or external
interrupt inputs. When the IMF (Interrupt master enable flag) is “1” (Interrupt
enable), the execution will resume with the acceptance of the interrupt, and the
operation will return to normal after the interrupt service is completed. When the
IMF is “0” (Interrupt disable), the execution will resume with the instruction
which follows the IDLE1 mode start instruction.
operation.
register 2 (SYSCR2).
feeding the clock to the peripheral circuits other than TBT. Then, upon detecting
the falling edge of the source clock selected with TBTCR<TBTCK>, the timing
generator starts feeding the clock to all peripheral circuits.
NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of
how TBTCR<TBTEN> is set. When IMF = “1”, EF7 (TBT interrupt individual
enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed.
When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
IDLE1 mode
IDLE0 mode
In this mode, both the CPU core and on-chip peripherals operate using the
The TMP86FM48 is placed in this mode after reset.
In this mode, the internal oscillation circuit remains active. The CPU and the
IDLE1 mode is started by SYSCR2<IDLE>, and IDLE1 mode is released to
In this mode, all the circuit, except oscillator and the time-base-timer, stops
This mode is enabled by setting “1” on bit TGHALT on the system control
When IDLE0 mode starts, the CPU stops and the timing generator stops
When returned from IDLE0 mode, the CPU restarts operating, entering
86FM48-12
TMP86FM48
2007-08-24