TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 112

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

SCL pin (Master 1)
SCL pin (Master 2)
SCL (Bus)
b.
t
width in the external clock which is input from SCL pin.
pulls down a clock pulse to low will, in the first place, invalidate a clock pulse of
another master device which generates a high-level clock pulse.
function ensures normal transfer even if there are two or more masters on the
same bus.
simultaneously exist on a bus.
the bus becomes the low level. After detecting this situation, Master 2 resets
counting a clock pulse in the high level and sets the SCL pin to the low level.
SCL pin to the high level. Since Master 2 holds the SCL line of the bus at the low
level, Master 1 waits for counting a clock pulse in the high level. After Master 2
sets a clock pulse to the high level at point “c” and detects the SCL line of the bus
at the high level, Master 1 starts counting a clock pulse in the high level. Then,
the master, which has finished the counting a clock pulse in the high level, pulls
Note: Since the I
t
t
fscl = 1/(t
SCKL
Clock synchronization
LOW
HIGH
Four or more machine cycles are required for both high and low levels of pulse
In the I
The serial bus interface circuit has a clock synchronization function. This
The example explains clock synchronization procedures when two masters
As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the
, t
= 2
= 2
SCKH
n
Low
n
high-speed mode, do not set SCK as the frequency that is over 100 kHz.
/fc
fc: High-frequency clock
/fc + 8/fc
t
SCKL
2
t
> 4 tcyc
+ t
C bus, in order to drive a bus with a wired AND, a master device which
HIGH
a
Figure 2.12.6 Clock Synchronization
HIGH
Count restart
t
SCKH
Figure 2.12.5 Clock Source
)
2
C of TMP86FM48 can not be used as the fast mode and the
t
LOW
86FM48-108
Note: tcyc = 4/fc (in NORMAL mode, IDLE mode)
b
Wait
SCK (Bits2 to 0 in the SBICRA)
c
Count start
1/fscl
000
001
010
011
100
101
110
Count reset
10
n
4
5
6
7
8
9
TMP86FM48
2007-08-24