TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 136

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

c.
The transmit/receive mode are selected by writing “10” to SIO1CR<SIOM>.
1. Starting the transmit/receive operation
2. During the transmit/receive operation
Transmit/receive mode
Transmit/receive mode is selected by writing “10” to SIO1CR<SIOM>. Serial
clock is selected by using SIO1CR<SCK>. Transfer direction is selected by
using SIO1CR<SIODIR>.
When a transmit data is written to the transmit buffer register (SIO1TDB),
SIO1SR<TXF> is cleared to “0”.
After SIO1CR<SIOS> is set to “1”, SIO1SR<SIOF> is set synchronously to the
falling edge of
The data is transferred sequentially starting from SO1 pin with the direction
of the bit specified by SIO1CR<SIODIR>, synchronizing with the
falling edge. And receiving operation also starts with the direction of the bit
specified by SIO1CR<SIODIR>, synchronizing with the
edge.
SIO1SR<SEF> is kept in high level between the first clock falling edge of
SIO1SR<TXF> is set to “1” at the rising edge of
written to the SIO1TDB is transferred to shift register. When 8-bit data has
been received, the received data is transferred to SIO1RDB from shift register,
then the INTSIO1 interrupt request occurs, synchronizing with setting
SIO1SR<RXF> to “1”.
Note 1:
Note 2:
When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0” and when
a data is read from SIO1RDB, SIO1SR<RXF> is cleared to “0”.
In internal clock operation, in case of the condition described below, the serial
clock stops to “H” level by an automatic-wait function when all of the bit set in
the data has been transmitted.
•
•
•
SCK1
Next transmit data is not written to SIO1TDB after reading a received
data from SIO1RDB
Received data is not read from SIO1RDB after writing a next transmit
data to SIO1TDB
Neither SIO1TDB nor SIO1RDB is accessed after transmission.
The automatic wait function is released by writing the next transmit data
to SIO1TDB after reading the received data from SIO1RDB, or reading
the received data from SIO1RDB after writing the next data to SIO1TDB.
Then, transmit/receive operation is restarted after maximum 1 cycle of
serial clock.
pin and eighth clock falling edge.
In internal clock operation, when the SIO1CR<SIOS> is set to “1”,
SIO1TDB is transferred to shift register after maximum 1-cycle of serial
clock frequency, then a serial clock is output from
In external clock operation, when the falling edge is input from
pin after SIO1CR<SIOS> is set to “1”, SIO1TDB is transferred to shift
register immediately. When the rising edge is input from
receive operation also starts.
SCK1
86FM48-132
pin.
SCK1
SCK1
pin after the data
SCK1
TMP86FM48
pin.
2007-08-24
pin's rising
SCK1
SCK1
SCK1
pin’s
pin,