TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 157

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.17.2
FLASH Control Register
EEPCR
(1FE0H)
MNPWDW
ATPWDW
EEPMD
EEPRS
Note 1: The EEPMD, EEPRS, and MNPWDW can be rewritten only when a program fetch is taking place in the RAM or
Note 2: To write to the FLASH, set the EEPMD with “0011B” in advance when a program fetch is taking place in the RAM
Note 3: To forcibly stop writing of FLASH, set the EEPRS to “1” when a program fetch is taking place in the RAM area.
Note 4: The ATPWDW functions only if the MNPWDW is “1”. If the MNPWDW is “0”, the power for the FLASH control
Note 5: When a STOP mode is executed, the power for the FLASH control circuit is turned off regardless of the setting of
Note 6: Executing a read instruction to the EEPCR register results in bit3 being read as undefined. Bit2 is always read as
Note 7: The following attention is necessary when the MNPWDW is set or cleared.
Control
(EEPSR) and FLASH write emulate time control register (EEPEVA).
BOOT-ROM area. If an attempt is made to rewrite the EEPCR register when a program is being executed in the
FLASH area, the EEPMD, EEPRS, and MNPWDW keep holding the previous data; they are not rewritten.
area. However, this processing is not required if a support program in the BOOT-ROM is used.
circuit is kept turned off regardless of the setting of the ATPWDW.
the ATPWDW. If the MNPWDW is “0”, entering/exiting the STOP mode allows the power for the FLASH control
circuit to be kept turned off.
“0”.
The FLASH is controlled by FLASH control register (EEPCR), FLASH status register
7
FLASH write enable control
(Write protect)
FLASH write forcible stop
Automatic power control for the
FLASH control circuit in the
IDLE0/1/2, SLEEP0/1/2 modes.
(This bit is available only when
MNPWDW is set to “1”.)
Software-based power control
for the FLASH control circuit
When the MNPWDW is
changed from “1” to “0”
When the MNPWDW is
changed from “0” to “1”
6
EEPMD
5
Figure 2.17.2 FLASH Control Register
Clear the interrupt master enable flag (IMF) to “0” in advance to disable an
interrupt. After that, do not set IMF to “1” during EEPSR<EWUPEN> = “0”.
If a watchdog timer is used as interrupt request, clear the binary counter for the
watchdog timer just before MNPWDW is changed from “1” to “0”.
When write to or read from the Flash memory, make sure that the
EEPSR<EWUPEN> is “1” by software. Once the MNPWDW is rewritten from
“0” to “1” by software, keep performing software-based polling until the
EEPSR<EWUPEN> becomes “1”.
4
1100: FLASH write disable
0011: FLASH write enable
Other values: Reserved
0: −
1: FLASH writing is forced to stop.
0: Automatic power shut down is executed in
1: Automatic power shut down is not executed
0: The power for the FLASH control circuit is
1: The power for the FLASH control circuit is
(The write data counter is initialized.)
* After writing “1” to EEPRS, it is
automatically cleared to “0”.
IDLE0/1/2 and SLEEP0/1/2 modes.
in IDLE0/1/2 and SLEEP0/1/2 modes. (The
power is always supplied in these modes.)
turned off.
turned on
86FM48-153
3
EEPRS
2
ATPWDW MNPWDW
1
0
Program Execution Area
(Initial value: 1100 *011)
BOOT
RAM/
R/W
TMP86FM48
2007-08-24
FLASH
Read
Read
R/W
only
only