TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 31

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

•
•
a.
b.
Start the IDLE0 and SLEEP0 modes
Release the IDLE0 and SLEEP modes
release mode.
enable-flag (EF7) for INTTBT and TBTCR<TBTEN>.
automatically cleared to “0” and the operation mode is returned to the mode
preceding IDLE0 and SLEEP0 modes. Before starting the IDLE0 or SLEEP0
mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to
“1”.
= “0”, the CPU wait period for stabilizing of the power supply of Flash control
circuit is added before the operation mode is returned to the preceding modes. The
CPU wait time of IDLE0 is 2
mode.
is setting by the TBTCR<TBTCK>. After the falling edge is detected, the program
operation is resumed from the instruction following the IDLE0 and SLEEP0
modes start instruction.
Interrupt release mode (IMF•EF7•TBTCR<TBTEN> = “1”)
is setting by the TBTCR<TBTCK> and INTTBT interrupt processing is started.
Note 1: IDLE0
Note 2: During CPU wait, though CPU operations remain halted, but the peripheral
Normal release mode (IMF•EF7•TBTCR<TBTEN> = “0”)
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed
Note 2: When a watchdog timer interrupt is generated immediately before
RESET
Stop (Disable) peripherals such as a timer counter.
When IDLE0 and SLEEP0 modes start, set SYSCR2<TGHALT> to “1”.
IDLE0 and SLEEP0 modes include a normal release mode and an interrupt
These modes are selected by interrupt master flag (IMF), individual interrupt
After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is
When the IDLE0 and SLEEP0 modes are started with the EEPCR<ATPWDW>
IDLE0 and SLEEP0 modes can also be released by inputting low level on the
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which
TBTCR<TBTEN> setting.
function operation is resumed. Therefore in this time, though the interrupt latch
might be set, interrupt operation is not executed until the CPU wait is finished.
pin. After releasing reset, the operation mode is started from NORMAL1
by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might
be the shorter than the period setting by TBTCR<TBTCK>.
IDLE0/SLEEP0 mode is started, the watchdog timer interrupt will be
processed but IDLE0/SLEEP0 mode will not be started.
and
SLEEP0
86FM48-27
10
/fc [s] and that of SLEEP0 mode is 2
modes
start/release
without
3
/fs [s].
reference
TMP86FM48
2007-08-24
to