TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 97

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Internal clock
Up counter
TC5DR
Timer F/F5
INTTC5
interrupt
PWM
pin output
TC5CK
(4) Pulse width modulation (PWM) output mode
000
001
010
011
100
101
110
constant intervals with a resolution of 8 bits. The counter counts up on the internal
source clock. If the timer value matches TC5DR, the timer F/F5 is inverted, and the
counter keeps-up counting. If an overflow is detected, the timer F/F5 is inverted again,
generating an INTTC5 interrupt. The P13 (
timer F/F5 output level.
timer when the PWM output is low may cause one cycle to become smaller than the set
value.
P13 port to “1”.
until one output cycle is completed even if TC5DR is overwritten; therefore, pulse
width can be altered continuously. Also, the first time, TC5DR is shifted by setting
TC5CR<TC5S> to “1” after data are loaded to TC5DR.
Note: In PWM mode, writing to the timer register TC5DR should be performed only right
0
The pulse width modulation (PWM) output mode is intended to output pulses at
At a reset or when the timer stops, the timer F/F5 is cleared to “0”. So, stopping the
To use the pulse width modulation (PWM) output mode, set the output latch of the
TC5DR is configured a 2-stage shift register and, during pulse width, will not switch
Match
n/n
1
Table 2.10.3 PWM Output Mode (Example: fc = 16 MHz)
after an INTTC5 interrupt occurs (Usually, within the INTTC5 interrupt service
routine). If writing to the timer register TC5DR occurs at the same timing as the
INTTC5 interrupt, pulses having a value other than the set value may be output
before another INTTC5 interrupt occurs, because an unstable value that is being
written is shifted.
Figure 2.10.4 PWM Output Mode Timing Chart
n
Resolution [ns]
n + 1
500
250
125
62.5
−
−
−
FF
NORMAL1/2, IDLE1/2 Mode
86FM48-93
0
1
Overwrite
n/m
1 cycle
n
PWM5
n + 1
Repeat Cycle [µs]
) pin outputs an inversion of the
128
64
32
16
FF
−
−
−
0
Shift
m/m
1
TMP86FM48
m − 1 m
2007-08-24