TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 27

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Note 1: EEPCR<ATPWDW> is a bit1 in EEPCR, which is a control bit of the power supply circuit for flash.
Note 2: During CPU wait, though CPU operations remain halted, the peripheral function operation is resumed.
(2) IDLE1/2 mode, SLEEP1/2 mode
(Normal release mode)
(SYSCR2) and maskable interrupts. The following status is maintained during these
modes.
a.
b.
c.
Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the
CPU wait is finished.
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2
The program counter holds the address 2 ahead of the instruction which starts
these modes.
continue to operate.
The data memory, CPU registers, program status word and port output latches
are all held in the status in effect before these modes were entered.
Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals
Figure 1.4.12 IDLE1/2, SLEEP1/2 Modes
No
No
“1”
the IDLE1/2 and SLEEP1/2
instruction which follows
modes start instruction
and SLEEP1/2 modes
CPU, WDT are halted
Interrupt processing
EEPCR<ATPWDW>
Starting IDLE1/2
Interrupt request
Execution of the
by instruction
Reset input
CPU wait
86FM48-23
IMF = 1
No
Yes
Yes (Interrupt release mode)
“0”
Yes
Reset
TMP86FM48
2007-08-24