TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 21

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

1.4.4
Operating Mode Control
(1) STOP mode
key-on wake-up input (STOP0 to STOP3) which is controlled by the STOP mode
release control register (STOPCR).
5) pin.
following status is maintained.
which can be selected with the SYSCR1<RELM>. Do not use any STOPx (x: 0 to 3) pin
input for releasing STOP mode in edge-sensitive mode.
period for stabilizing of the power supply of Flash control circuit is executed after in the
STOP warming-up time.
Note 1: The STOP mode can be released by either the STOP or key-on wake-up pin
Note 2: During stop period (from start of STOP mode to end of warm-up), due to changes in
a.
b.
c.
d. The program counter holds the address 2 ahead of the instruction (e.g. [SET
a.
STOP mode is controlled by the system control register 1, the
The
STOP mode is started by setting SYSCR1<STOP> to “1”. During STOP mode, the
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of
When the STOP mode is started with the EEPCR<MNPWDW> = “1”, the CPU wait
(SYSCR1).7]) which started STOP mode.
The data memory, registers, the program status word and port output latches are
all held in the status in effect before STOP mode was entered.
Level-sensitive release mode (RELM = “1”)
the STOPx (x: 0 to 3) pin input which is enabled by STOPCR. This mode is used
for capacitor back-up when the main power supply is cut off and long term battery
back-up.
mode will not place in STOP mode but instead will immediately start the release
sequence (Warm-up). Thus, to start STOP mode in the level-sensitive release
mode, it is necessary for the program to first confirm that the
low. The following two methods can be used for confirmation.
Oscillations are turned off, and all internal operations are halted.
The prescaler and the divider of the timing generator are cleared to “0”.
STOP
In this mode, STOP mode is released by setting the
When the
a.
b.
(STOP0 to STOP3). However, because the
wake-up and can not inhibit the release input, the
releasing STOP mode.
the external interrupt pin signal, interrupt latches may be set to “1” and interrupts
may be accepted immediately after STOP mode is released. Before starting STOP
mode, therefore, disable interrupts. Also, before enabling interrupts after STOP
mode is released, clear unnecessary interrupt latches.
Testing a port P20.
Using an external interrupt input
input).
pin is also used both as a port P20 and an
STOP
pin input is high, executing an instruction which starts STOP
86FM48-17
INT5
STOP
(
INT5
INT5
pin is different from the key-on
STOP
is a falling edge-sensitive
STOP
(External interrupt input
pin must be used for
STOP
pin high or setting
STOP
pin input and
TMP86FM48
2007-08-24
pin input is