TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 72

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(0021,0020H)
(0023,0022H)
TC1DRA
TC1DRB
TC1CR
(001FH)
R/W
R/W
2.7.2
MPPG1 PPG output control
TC1CK
ACAP1
METT1
MCAP
TC1M
TC1S
TFF1
Note:
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: The timer register consists of two shift registers. A value set in the timer register is put in effect at the rising
Note 3: Set the mode, source clock, PPG control and timer F/F control when TC1 stops (TC1S = 00).
Note 4: Auto-capture can be used in only timer, event counter, and window modes.
Note 5: Values to be loaded to timer registers must satisfy the following condition.
Note 6: Always write “0” to TFF1 except PPG output mode.
Note 7: Writing to the TC1DRB is not possible unless TC1 is set to the PPG output mode.
Note 8: On entering STOP mode, the TC1 start control (TC1S) is cleared to “00” automatically. So, the timer stops.
Note 9: Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's
TFF1
Control
16-bit timer registers (TC1DRA and TC1DRB).
15
TC1 operating mode select
TC1 source clock select [Hz]
TC1 start control
Auto capture control
Pulse width measurement
mode control
External trigger timer mode
control
Time F/F1 control
7
The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two
MPPG1
ACAP1
MCAP1
METT1
14
TC1DRB should not be written except PPG mode.
edge of the first source clock pulse that occurs after the upper data (TC1DRAH and TC1DRBH) are written.
Therefore, the lower byte must be written before the upper byte (it is recommended that a 16-bit access
instruction be used in writing). Writing only the lower data (TC1DRAL and TC1DRBL) does not put the
setting of the timer register in effect.
TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (others)
Once the STOP mode has been released, to start using the timer counter, set TC1S again.
read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture
enabled condition.
6
13
5
TC1S
TC1DRAH (0021H)
TC1DRBH (0023H)
12
4
11
3
TC1CK
00: Timer/external trigger timer/event counter mode
01: Window mode
10: Pulse width measurement mode
11: PPG (Programmable pulse generate) output mode
00
01
10
11
00: Stop and counter clear
01: Command start
10: External trigger start at the rising edge
11: External trigger start at the falling edge
0: Auto-capture disable
0: Double edge capture
0: Trigger start
0: Continuous pulse generation 1: One-shot
0: Clear
External clock (TC1 pin input)
10
2
DV7CK = 0
86FM48-68
1
9
NORMAL1/2, IDLE1/2 mode
fc/2
fc/2
fc/2
TC1M
11
7
3
0
8
(Initial value: 0000 0000)
7
1: Auto-capture enable
1: Single edge capture
1: Trigger start and stop
1: Set
DV7CK = 1
6
fs/2
fc/2
fc/2
Timer Extend Event Window Pulse PPG
(Initial value: 1111 1111 1111 1111)
(Initial value: 1111 1111 1111 1111)
3
7
3
○
○
×
×
5
TC1DRAL (0020H)
TC1DRBL (0022H)
○
○
○
×
4
SLOW1/2, SLEEP1/2
○
○
○
×
3
○
○
○
×
mode
fs/2
−
−
2
3
○
○
○
×
TMP86FM48
2007-08-24
○
○
○
○
1
R/W
0