TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 154

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Rewriting the EEPCR register<EEPMD, EEPRS,
MNPWDW>
Accessing the EEPEVA register
FLASH write time
(The emulation chip is written to emulation
memory instead of FLASH)
Executing a read instruction/fetch to the 8000H to
FFFFH area when EEPSR<BFBUSY> = “1”
Executing a write instruction to
the 8000H to 81FFH area when
EEPCR<EEPMD> = “0011”,
EEPSR<EWUPEN> = “1” and
EEPSR<BFBUSY> = “0”.
Executing a write instruction to
the 8200H to FFFFH area
when EEPCR<EEPMD> =
“0011”, EEPSR<EWUPEN> =
“1” and EEPSR<BFBUSY> =
“0”.
Data memory (8000H to 81FFH)
BOOT-ROM
Operating voltage
2.16.3
Differences among Product Series
emulation chip (TMP86C948) as listed below. See 2.17.2 “Control ” for explanations about
the control registers.
The specifications of the FLASH product (TMP86FM48) are different from those of the
MCU mode
Serial PROM
mode
MCU mode
Serial PROM
mode
It is possible to rewrite the EEPCR register only when the program
execution area in use is RAM/BOOT-ROM.
It is possible only to write- and
read-access the EEPEVA register.
The writing to this register does not
affect the function.
Typically 4 ms
(Independent of the system clock)
If EEPSR<BFBUSY> = “1”, executing a read instruction/fetch to the FLASH
area causes FFH to be read regardless of what the current ROM data is.
Fetching FFH results in a software interrupt occurring.
The EEPSR<BFBUSY> is set to “1” (Write enabled).
The EEPSR<BFBUSY> stays at “0” (Write disabled).
The EEPSR<BFBUSY> is set to “1” (write enabled).
512 bytes of FLASH are included in
the 8000H to 81FFH area.
2 Kbytes are included in the 3800H to 3FFFH area.
VDD = 1.8 to 3.6 V
86FM48-150
FLASH Product
(TMP86FM48)
In the debugger memory
window, it is impossible to
rewrite the EEPCR register.
The time required to emulate
FLASH writing is put under
control.
The FLASH write time is set up
using the EEPEVA register
(Dependent on the system
clock).
The debugger memory window
always displays ROM data.
In the debugger memory
window, it is possible to rewrite
the 8200H to FFFFH area (The
EEPSR<BFBUSY> remains
unchanged).
512 bytes of emulation memory
are included in the 8000H to
81FFH area. (Turning off the
power for the emulation chip
erases data in the emulation
memory.)
VDD = 1.8 to 3.3 V
Emulation Chip
(TMP86C948)
TMP86FM48
2007-08-24