TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 57

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

P5OUTCR
Read only
(000D
(0005
(1FF2
P5PRD
P5DR
2.2.5
R/W
H
H
H
)
)
)
P5OUTCR
Port P5 (P52 to P50)
output and serial bus interface input/output. (N-ch high current output) It can be selected
whether output circuit of P5 port is CMOS output or a sink open drain individually, by
setting the output circuit control (P5OUTCR). When a corresponding bit of P5OUTCR is
cleared to “0”, the output circuit is selected to a sink open drain and when a corresponding
bit of P5OUTCR is set to “1”, the output circuit is selected to a CMOS output.
latch (P5DR) should be set to “1” and its corresponding P5OUTCR bit should be cleared to
“0”.
respective P5DR should be set to “1”.
“1” and P5OUTCR of P50 and P51 should be cleared to “0” as a sink open drain output.
respective address. When read the output latch data, the P5DR should be read and when
read the terminal input data, the P5PRD register should be read.
are unstable.
7
Port P5 is an 3-bit input/output port which is also used as a timer/counter output, divider
When used as an input port or a serial bus interface input/output, the respective output
When used as a secondary function output (Timer/counter output or divider output), the
When used as a serial bus interface input/output, P5DR of P50 and P51 should be set to
During reset, the P5DR is initialized to “1” and P5OUTCR is initialized to “0”.
P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their
If a read instruction is executed for P5DR, P5OUTCR and P5PRD, read data of bits 7 to 3
Data input (P5PRD)
Data output (P5DR)
Data input (P5DR)
P5OUTCRi input
Control output
Port P5 output circuit control
(Set for each bit individually)
6
P5OUTCRi
OUTEN
STOP
5
4
D
Output latch
Figure 2.2.7 Port 5
D
3
86FM48-53
Q
0: Sink open-drain output
1: CMOS output
Q
P52
P52
2
DVO
SDA
P51
P51
1
SCL
P50
PPG
P50
0
(Initial value: **** *111)
*: Don’t care
(Initial value: **** *000)
*: Don’t care
Note: i = 2 to 0
P5i
TMP86FM48
2007-08-24
R/W