TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 86

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

TC2 pin input
Internal clock
Up counter
TC2DR
INTTC2 interrupt
(3) Window mode
TC2 external pin input (Window pulse) is “H” level. The contents of TC2DR are
compared with the contents of up counter. If a match found, an INTTC2 interrupt is
generated, and the up-counter is cleared.
selected internal clock.
Note: In the window mode, before the SLOW/SLEEP mode is entered, the timer should
In this mode, counting up performed on the rising edge of an internal clock during
The maximum applied frequency (TC2 input) must be considerably slower than the
Example: Generates an interrupt, inputting “H” level pulse width of 120 ms or more.
be halted by setting TC2CR<TC2S> to “0”.
n
0
(at fc = 16 MHz, DV7CK = 0)
Figure 2.8.3 Window Mode Timing Chart
LDW
DI
SET
EI
LD
LD
1
2
(TC2DR), 00EAH
(EIRE). 4
(TC2CR), 00000101B
(TC2CR), 00100101B
86FM48-82
n − 3
n − 2
;
;
;
;
;
;
Match detect
Sets TC2DR (120 ms ÷ 2
IMF = “0”
Enables INTTC2 interrupt
IMF = “1”
TC2CK ← “001”, TC1M ← “1”
Starts TC2
n − 1 n 0
Counter clear
1
TMP86FM48
13
2
2007-08-24
/fc = 00EAH)
3