TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 18

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(3) STOP mode
operations to be halted. The internal status immediately prior to the halt is held with a
lowest power consumption during STOP mode.
released by a inputting (either level-sensitive or edge-sensitive can be programmably
selected) to the
After the warm-up period is completed, the execution resumes with the instruction
which follows the STOP mode start instruction.
f.
g.
In this mode, the internal oscillation circuit is turned off, causing all system
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is
status under the SLEEP2 mode is same as that under the SLEEP1 mode, except
for the oscillation circuit of the high-frequency clock.
operation.
register 2 (SYSCR2).
feeding the clock to the peripheral circuits other than TBT. Then, upon detecting
the falling edge of the source clock selected with TBTCR<TBTCK>, the timing
generator starts feeding the clock to all peripheral circuits.
SLOW1 mode back again. SLEEP0 mode is entered and returned regardless of
how TBTCR<TBTEN> is set. When IMF = “1”, EF7 (TBT interrupt individual
enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed.
When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.
SLEEP2 mode
SLEEP0 mode
Note 1: When the IDLE0/1/2 and SLEEP0/1/2 modes are started with the
Note 2: When the STOP mode is started with the EEPCR<MNPWDW> = “1”, the CPU
The SLEEP2 mode is the IDLE mode corresponding to the SLOW2 mode. The
In this mode, all the circuit, except oscillator and the time-base-timer, stops
This mode is enabled by setting “1” on bit TGHALT on the system control
When SLEEP0 mode starts, the CPU stops and the timing generator stops
When returned from SLEEP0 mode, the CPU restarts operating, entering
EEPCR<ATPWDW> = “0”, the CPU wait period for stabilizing of the power
supply of Flash control circuit is executed after being released from these
mode.
wait period for stablizing of the power supply of Flash control circuit is
executed after in the STOP warm-up time.
STOP
pin or key on wake up pin input which is enabled by STOPCR.
86FM48-14
TMP86FM48
2007-08-24