TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 15

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

TBTCR
(0036
Main system clock
H
)
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fc: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the
Note 5: When STOP mode is entered from NORMAL 1/2 mode, the DV7CK setting is ineffective during the
(DVOEN)
(2) Machine cycle
DV7CK
7
State
main system clock.
total of 10 different types of instructions for the TLCS-870/C series: ranging from
1-cycle instructions which require one machine cycle for execution to 10-cycle
instructions which require 10 machine cycles for execution.
system clock.
divider.
warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during
this period.
Instruction execution and peripheral hardware operation are synchronized with the
The minimum instruction execution unit is called an “machine cycle”. There are a
A machine cycle consists of 4 states (S0 to S3), and each state consists of one main
Selection of input to the 7th
stage of the divider
1/fc or 1/fs [s]
6
(DVOCK)
S0
Figure 1.4.4 Timing Generator Control Register
5
Machine cycle
S1
DV7CK
4
Figure 1.4.5 Machine Cycle
(TBTEN)
S2
3
86FM48-11
0: fc/2
1: fs
8
2
[Hz]
S3
(TBTCK)
1
S0
0
S1
(Initial value: 0000 0000)
S2
S3
TMP86FM48
2007-08-24
R/W