TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 169

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Address
8030H
8040H
8050H
8060H
8070H
00H
10H
20H
30H
00H
10H
20H
30H
0
0
01H
11H
21H
31H
01H
11H
21H
31H
1
1
(2) Method of specifying an address for a write to the FLASH
Note: If the BFBUSY is “1”, executing a read instruction or fetch to the FLASH area
02H
12H
22H
32H
02H
12H
22H
32H
address of the first-byte data. The first-byte data is stored at the first address of
the temporary data buffer. If the data to be written is, for example, 8040H, page 1
is selected, and the data is stored at the first address of the temporary data buffer.
Even if the 6 low-order bits of the specified address is not 000000B, the first-byte
data is always stored at the first address of the data buffer.
FLASH area (for the MCU mode, 8000 to 81FFH and, for the serial PROM mode,
8000H to FFFFH). The write data bytes are stored in the temporary data buffer in
the sequence they are written, regardless of what address is specified. Usually, the
address that is the same as the first-byte is specified for the second and
subsequent address. A 16-bit transfer instruction (LDW) can also be used for
writing to the temporary data buffer.
Example: Data bytes 00H to 3FH are written to page 1.
2
2
sLOOP1:
sLOOP2:
The FLASH page to be written is specified by the 10 high-order bits of the
Any address can be specified as the second and subsequent address within
Figure 2.17.9 Data Buffer and Write Page (Example)
03H
13H
23H
33H
03H
13H
23H
33H
3
3
causes “FFH” to be read. Fetching “FFH” results in a software interrupt
occurring.
(Figure 2.17.8 shows the example of data buffer and pages.)
04H
14H
24H
34H
04H
14H
24H
34H
4
4
DI
LD
LD
LD
LD
LD
INC
CMP
JR
TEST
JRS
LD
05H
15H
25H
35H
05H
15H
25H
35H
5
5
06H
16H
26H
36H
06H
16H
26H
36H
6
6
86FM48-165
C,00H
HL,EEPCR
IX,8040H
(HL),3BH
(IX),C
C
C,40H
NZ,sLOOP1
(EEPSR).0
F,sLOOP2
(HL),0CBH
Temporary
data buffer
07H
37H
07H
37H
7
7
Page 1
08H
38H
08H
38H
8
8
09H
19H
29H
39H
09H
19H
29H
39H
9
9
0AH
1AH
2AH
3AH
0AH
1AH
2AH
3AH
A
A
;
;
;
;
;
;
;
;
;
0BH
1BH
2BH
3BH
0BH
1BH
2BH
3BH
Disable an interrupt (IMF ← “0”)
Specify the EEPCR register address.
Specify a write address.
Specify the EEPCR
Store data to the temporary data buffer.
(A write page is selected when the first
byte is written.)
C = C + 1
Jump to sLOOP1 if C is not 40H
Jump to sLOOP2 if EEPSR<BFBUSY> =
“1”.
Specify the EEPCR
B
B
0CH
1CH
2CH
3CH
0CH
1CH
2CH
3CH
C
C
0DH
1DH
2DH
3DH
0DH
1DH
2DH
3DH
D
D
0EH
1EH
2EH
3EH
0EH
1EH
2EH
3EH
E
E
TMP86FM48
2007-08-24
0FH
1FH
2FH
3FH
0FH
1FH
2FH
3FH
F
F