TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 76

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

TC1 pin input
Internal clock
Up counter
TC1DRA
INTTC1 interrupt
TC1 pin input
Internal clock
Up counter
TC1DRA
INTTC1 interrupt
TC1 pin input
Up counter
TC1DRA
INTTC1
interrupt
?
(3) Event counter mode
?
Count start
n
falling edge can be selected with the external trigger TC1CR<TC1S>). The contents of
TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1
interrupt is generated, and the counter is cleared. After the counter is cleared, the up
counter starts counting by TC1 input edge. Match detect is executed on other edge of
count-up. A match can not be detected and INTTC1 is not generated when the pulse is
still in same state. Two or more machine cycles are required for both the “H” and “L”
levels of the pulse width.
TC1DRB (Auto-capture function). Use the auto-capture function in the operative
condition of TC1. A captured value may not be fixed if it's read after the execution of
the timer stop or auto-capture disable. Read the capture value in a capture enabled
condition. Since the up-counter value is captured into TC1DRB by the source clock of
up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value,
wait at least one cycle of the internal source clock before reading TC1DRB for the first
time.
0
In this mode, events are counted at the edge of the TC1 pin input (either the rising or
Setting TC1CR<ACAP1> to “1” transfers the current contents of up counter to
Count start
0
n
Count start
n
0
Figure 2.7.4 External Trigger Timer Mode Timing Chart
Trigger
1
Trigger
Figure 2.7.5 Event Counter Mode Timing Chart
1
2
1
3
2
2
Count clear
(a) Trigger start (METT1 = 0)
(b) Trigger start and Stop (METT1 = 1)
m
3
86FM48-72
Trigger
0
Count start
Match detect
Match detect
n − 1
Trigger
n − 1 n
1
n
0
Counter clear
Match detect
Counter clear
n − 2
Count start
0
n − 1 n
1
Trigger
1
0
Counter clear
2
2
TMP86FM48
3
TC1S = 10 at
the rising edge
2007-08-24
Note: m < n
TC1S = 10 at
the rising
edge
TC1S = 10
at the rising
edge