TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 89

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.9.3
Table 2.9.1 Source Clock (Internal clock) for Timer/Counter 3 (Example: at fc = 16 MHz)
TC3CK
Function
(1) Timer mode
000
001
010
011
100
101
110
The timer/counter 3 has three operating modes: timer, event counter, and capture mode.
compared with the contents of up counter. If a match is found, a timer/counter 3
interrupt (INTTC3) is generated, and the up counter is cleared.
TC3CR<ACAP> to “1” (Auto-capture function). The contents of up counter can be
easily confirmed by executing the read instruction (RD instruction) of TC3DRB.
Loading the contents of up counter is not synchronized with counting up. The contents
of over flow (FFH) and 00H can not be loaded correctly. It is necessary to consider the
count cycle.
In this mode, the internal clock is used for counting up. The contents of TC3DRA are
The current contents of up counter are loaded into TC3DRB by setting
Resolution
512.0
256.0
128.0
Clock
Counter
TC3DRB
[µs]
64.0
32.0
16.0
8.0
DV7CK = 0
NORMAL1/2, IDLE1/2 Mode
Maximum
Setting
130.6
Time
[ms]
65.3
32.6
16.3
8.2
4.1
2.0
FE
Resolution
86FM48-85
FE
976.6
488.3
244.1
122.0
[µs]
61.0
16.0
8.0
FF
DV7CK = 1
00
FF
Maximum
Setting
Time
249.0
124.5
[ms]
62.3
31.1
15.6
01
4.1
2.0
01
Resolution
976.6
488.3
244.1
122.0
SLOW1/2 Mode
[µs]
61.0
−
−
Maximum
Setting
249.0
124.5
Time
[ms]
62.3
31.1
15.6
−
−
TMP86FM48
2007-08-24