TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 52

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

P0OUTCR
Read only
(1FED
(0000
(000A
P0PRD
P0DR
2.2.1
R/W
H
H
H
)
)
)
P0OUTCR
Port P0 (P07 to P00)
serial interface input/output, timer/counter input and UART input/output. It can be
selected whether output circuit of P0 port is CMOS output or a sink open drain individually,
by setting the output circuit control (P0OUTCR). When a corresponding bit of P0OUTCR is
cleared to “0”, the output circuit is selected to a sink open drain and when a corresponding
bit of P0OUTCR is set to “1”, the output circuit is selected to a CMOS output.
serial interface input, timer/counter input or UART input), the respective output latch
(P0DR) should be set to “1” and its corresponding P0OUTCR bit should be cleared to “0”.
respective P0DR should be set to “1”.
respective address. When read the output latch data, the P0DR should be read and when
read the terminal input data, the P0PRD register should be read.
SCK1
P07
P07
7
Port P0 is an 8-bit input/output port which is also used as an external interrupt input,
When used as an input port or a secondary function input (External interrupt input,
When used as a secondary function output (Serial interface output or UART output), the
During reset, the P0DR is initialized to “1” and P0OUTCR is initialized to “0”.
P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their
Data input (P0PRD)
Data output (P0DR)
Data input (P0DR)
P0OUTCRi input
Control output
SO1
Control input
P06
TxD
P06
Port P0 output circuit control
(Set for each bit individually)
P0OUTCRi
6
OUTEN
STOP
RxD
P05
P05
SI1
5
P04
P04
4
D
Output latch
Figure 2.2.2 Port 0
D
P03
TC2
P03
3
86FM48-48
Q
0: Sink open-drain output
1: CMOS output
Q
INT2
P02
P02
2
INT1
P01
P01
1
INT0
P00
P00
0
(Initial value: 1111 1111)
(Initial value: 0000 0000)
Note: i = 7 to 0
P0i
TMP86FM48
2007-08-24
R/W