TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 17

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(2) Dual-clock mode
P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main
system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2
modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The
machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 µs
at fs = 32.768 kHz) in the SLOW and SLEEP modes.
dual-clock mode, the low-frequency oscillator should be turned on at the start of a
program.
a.
b.
c.
d.
e.
Both the high-frequency and low-frequency oscillation circuits are used in this mode.
The TLCS-870/C is placed in the single-clock mode during reset. To use the
NORMAL2 mode
peripherals operate using the high-frequency clock and/or low-frequency clock.
SLOW2 mode
the high-frequency clock and the low-frequency clock are operated. On-chip
peripherals are triggered by the low-frequency clock. As the SYSCK on SYSCR2
becomes “0”, the hardware changes into NORMAL2 mode. As the XEN on
SYSCR2 becomes “0”, the hardware changes into SLOW1 mode. Do not clear
XTEN to “0” during SLOW2 mode.
the high-frequency clock. The CPU core and on-chip peripherals operate using the
low-frequency clock.
XEN bit on the system control register 2 (SYSCR2). In SLOW1 and SLEEP mode,
the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th
stages is also stopped.
watchdog timer are halted; however, on-chip peripherals remain active (Operate
using the high-frequency clock and/or the low-frequency clock). Starting and
releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation
returns to NORMAL2 mode.
SLEEP1 mode
active. The CPU, the watchdog timer, and the internal oscillation circuit of the
high-frequency clock are halted; however, on-chip peripherals remain active
(Operate using the low-frequency clock). Starting and releasing of SLEEP mode
are the same as for IDLE1 mode, except that operation returns to SLOW mode. In
SLOW and SLEEP mode, the input clock to the 1st stage of the divider is stopped;
output from the 1st to 6th stages is also stopped.
SLOW1 mode
IDLE2 mode
In this mode, the CPU core operates with the high-frequency clock. On-chip
In this mode, the CPU core operates with the low-frequency clock, while both
This mode can be used to reduce power-consumption by turning off oscillation of
Switching back and forth between SLOW1 and SLOW2 modes are performed by
In this mode, the internal oscillation circuit remain active. The CPU and the
In this mode, the internal oscillation circuit of the low-frequency clock remains
86FM48-13
TMP86FM48
2007-08-24