TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 132

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

SIO1CR<SIOS>
SIO1SR<SIOF>
SIO1SR<SEF>
Input
SO1 pin
TXF
SIO1SR<TXERR>
INTSIO1
interrupt
request
SIO1TDB
SIO1CR
<SIOINH>
SCK1
pin
Writing transmit
data A
A
4. Transmit error processing
A7
Figure 2.13.12 Example of Transmit Error Processing
Transmit errors occur on the following situation.
•
Writing transmit
data B
A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1
Start shift
operation
Shift operation starts before writing next transmit data to SIO1TDB in
external clock operation.
If transmit errors occur during transmit operation, SIO1SR<TXERR> is
set to “1” immediately after starting shift operation. Synchronizing with
the next serial clock falling edge, INTSIO1 interrupt request is
generated.
If shift operation starts before writing data to SIO1TDB after SIO1CR
<SIOS> is set to “1”, SIO1SR<TXERR> is set to “1” immediately after
shift operation is started and then INTSIO1 interrupt request is
generated.
SO1 pin is kept in high level when SIO1SR<TXERR> is set to “1”. When
transmit error occurs, transmit operation must be forcibly stop by
writing SIO1CR<SIOINH> to “1”. In this case, SIO1CR<SIOS>, SIO1SR
register, SIO1RDB register and SIO1TDB register are initialized.
B
86FM48-128
Start shift
operation
B0
Start shift
operation
Unknown
TMP86FM48
2007-08-24